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Fabio Somenzi - Publications

Affiliations: 
Electrical Engineering University of Colorado, Boulder, Boulder, CO, United States 
Area:
Electronics and Electrical Engineering
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30 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Nanshi K, Somenzi F. Using abstraction to guide the search for long error traces Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 453-466. DOI: 10.1109/Tcad.2012.2228266  0.641
2013 Sohail S, Somenzi F. Safety first: a two-stage algorithm for the synthesis of reactive systems International Journal On Software Tools For Technology Transfer. 15: 433-454. DOI: 10.1007/S10009-012-0224-3  0.487
2010 Han H, Somenzi F, Jin H. Making Deduction More Effective in SAT Solvers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1271-1284. DOI: 10.1109/Tcad.2010.2049135  0.63
2007 Kim H, Jin H, Somenzi F. Disequality Management in Integer Difference Logic via Finite Instantiations Journal On Satisfiability, Boolean Modeling and Computation. 3: 47-66. DOI: 10.3233/Sat190029  0.528
2006 Awedh M, Somenzi F. Termination criteria for bounded model checking: Extensions and comparison Electronic Notes in Theoretical Computer Science. 144: 51-66. DOI: 10.1016/J.Entcs.2005.07.019  0.734
2005 Jin H, Somenzi F. An Incremental Algorithm to Check Satisfiability for Bounded Model Checking Electronic Notes in Theoretical Computer Science. 119: 51-65. DOI: 10.1016/J.Entcs.2004.06.062  0.572
2005 Li B, Wang C, Somenzi F. Abstraction refinement in symbolic model checking using satisfiability as the only decision procedure International Journal On Software Tools For Technology Transfer. 7: 143-155. DOI: 10.1007/S10009-004-0169-2  0.471
2005 Ward D, Somenzi F. Automatic generation of hints for symbolic traversal Lecture Notes in Computer Science. 207-221. DOI: 10.1007/11560548_17  0.441
2003 Li B, Wang C, Somenzi F. A Satisfiability-Based Approach to Abstraction Refinement in Model Checking Electronic Notes in Theoretical Computer Science. 89: 608-622. DOI: 10.1016/S1571-0661(05)82546-0  0.485
2003 Gurumurthy S, Kupferman O, Somenzi F, Vardi MY. On Complementing Nondeterministic Büchi Automata Lecture Notes in Computer Science. 96-110. DOI: 10.1007/978-3-540-39724-3_10  0.434
2001 Drechsler R, Gunther W, Somenzi F. Using lower bounds during dynamic BDD minimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 51-57. DOI: 10.1109/43.905674  0.405
2001 Somenzi F. Symbolic State Exploration Electronic Notes in Theoretical Computer Science. 23: 46-56. DOI: 10.1016/S1571-0661(04)80668-6  0.366
2001 Somenzi F. Efficient manipulation of decision diagrams International Journal On Software Tools For Technology Transfer. 3: 171-181. DOI: 10.1007/S100090100042  0.321
2000 Meinel C, Somenzi F, Theobald T. Linear sifting of decision diagrams and its application in synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 521-533. DOI: 10.1109/43.845077  0.378
1999 Ravi K, Somenzi F. Hints to accelerate Symbolic Traversal Lecture Notes in Computer Science. 250-264. DOI: 10.1007/3-540-48153-2_19  0.458
1998 Macii E, Pedram M, Somenzi F. High-level power modeling, estimation, and optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 1061-1079. DOI: 10.1109/43.736181  0.304
1997 Macii E, Plessier B, Somenzi F. Formal verification of digital systems by automatic reduction of data paths Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1136-1156. DOI: 10.1109/43.662676  0.304
1997 Iris Bahar R, Cho H, Hachtel GD, Macii E, Somenzi F. Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1101-1115. DOI: 10.1109/43.662674  0.328
1996 Hachtel GD, Macii E, Pardo A, Somenzi F. Markovian analysis of large finite state machines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1479-1493. DOI: 10.1109/43.552081  0.384
1996 Cho H, Hachtel GD, Macii E, Plessier B, Somenzi F. Algorithms for approximate FSM traversal based on state space decomposition Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1465-1478. DOI: 10.1109/43.552080  0.375
1996 Cho H, Hachtel GD, Macii E, Poncino M, Somenzi F. Automatic state space decomposition for approximate FSM traversal based on circuit analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1451-1464. DOI: 10.1109/43.552079  0.37
1993 Cho H, Hachtel GD, Somenzi F. Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 935-945. DOI: 10.1109/43.238030  0.345
1993 Cho H, Jeong SW, Somenzi F, Pixley C. Synchronizing sequences and symbolic traversal techniques in test generation Journal of Electronic Testing. 4: 19-31. DOI: 10.1007/Bf00971937  0.376
1992 Hachtel GD, Rho JK, Somenzi F, Jacoby R. Exact and heuristic algorithms for the minimization of incompletely specified state machines . 184-191. DOI: 10.1109/43.259940  0.399
1988 Gai S, Montessoro PL, Somenzi F. MOZART: a concurrent multilevel simulator Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 7: 1005-1016. DOI: 10.1109/43.7799  0.384
1987 Gai S, Somenzi F, Ulrich E. Advances in Concurrent Multilevel Simulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 1006-1012. DOI: 10.1109/Tcad.1987.1270341  0.351
1987 Gai S, Somenzi F, Spalla M. Fast and Coherent Simulation with Zero Delay Elements Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 85-93. DOI: 10.1109/Tcad.1987.1270249  0.355
1985 Somenzi F, Gai S, Mezzalama M, Prinetto P. Testable design with PLA macros Microprocessing and Microprogramming. 15: 119-128. DOI: 10.1016/0165-6074(85)90070-5  0.427
1985 Gai S, Somenzi F, Spalla M. Zero delay elements in logic simulation Microprocessing and Microprogramming. 16: 335-339. DOI: 10.1016/0165-6074(85)90025-0  0.355
1984 Somenzi F, Gai S, Mezzalama M, Prinetto P. PART: Programmable Array Testing Based on a Partitioning Algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 3: 142-149. DOI: 10.1109/Tcad.1984.1270068  0.395
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