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Turbo Majumder, Ph.D. - Publications

Affiliations: 
2013 Electrical Engineering Washington State University, Pullman, WA, United States 
Area:
Computer Engineering
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14 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Li X, Duraisamy K, Baylon J, Majumder T, Wei G, Bogdan P, Heo D, Pande PP. A Reconfigurable Wireless NoC for Large Scale Microbiome Community Analysis Ieee Transactions On Computers. 66: 1653-1666. DOI: 10.1109/Tc.2017.2706278  0.606
2017 Paul S, Honkote V, Kim RG, Majumder T, Aseron PA, Grossnickle V, Sankman R, Mallik D, Wang T, Vangal S, Tschanz JW, De V. A Sub-cm 3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications Ieee Journal of Solid-State Circuits. 52: 961-971. DOI: 10.1109/Jssc.2016.2638465  0.31
2016 Li X, Duraisamy K, Bogdan P, Majumder T, Pande PP. Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2528121  0.66
2015 Majumder T, Pande PP, Kalyanaraman A. On-chip network-enabled many-core architectures for computational biology applications Proceedings -Design, Automation and Test in Europe, Date. 2015: 259-264.  0.659
2015 Majumder T, Li X, Bogdan P, Pande P. NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions Proceedings -Design, Automation and Test in Europe, Date. 2015: 1102-1107.  0.395
2014 Majumder T, Pande PP, Kalyanaraman A. Hardware accelerators in computational biology: Application, potential, and challenges Ieee Design and Test. 31: 8-18. DOI: 10.1109/Mdat.2013.2290118  0.67
2014 Majumder T, Pande PP, Kalyanaraman A. Wireless NoC platforms with dynamic task allocation for maximum likelihood phylogeny reconstruction Ieee Design and Test. 31: 54-64. DOI: 10.1109/Mdat.2013.2288778  0.617
2013 Majumder T, Pande PP, Kalyanaraman A. Network-on-chip with long-range wireless links for high-throughput scientific computation Proceedings - Ieee 27th International Parallel and Distributed Processing Symposium Workshops and Phd Forum, Ipdpsw 2013. 781-790. DOI: 10.1109/IPDPSW.2013.72  0.679
2013 Majumder T, Pande PP, Kalyanaraman A. High-throughput, energy-efficient network-on-chip-based hardware accelerators Sustainable Computing: Informatics and Systems. 3: 36-46. DOI: 10.1016/J.Suscom.2013.01.001  0.701
2012 Majumder T, Borgens ME, Pande PP, Kalyanaraman A. On-chip network-enabled multicore platforms targeting maximum likelihood phylogeny reconstruction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1061-1073. DOI: 10.1109/Tcad.2012.2188401  0.67
2012 Majumder T, Sarkar S, Pande PP, Kalyanaraman A. NoC-based hardware accelerator for breakpoint phylogeny Ieee Transactions On Computers. 61: 857-869. DOI: 10.1109/Tc.2011.100  0.651
2011 Majumder T, Pande P, Kalyanaraman A. Accelerating maximum likelihood based phylogenetic kernels using network-on-chip Proceedings - Symposium On Computer Architecture and High Performance Computing. 17-24. DOI: 10.1109/SBAC-PAD.2011.17  0.468
2010 Sarkar S, Majumder T, Kalyanaraman A, Pande PP. Hardware accelerators for biocomputing: A survey Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 3789-3792. DOI: 10.1109/ISCAS.2010.5537736  0.662
2010 Majumder T, Sarkar S, Pande P, Kalyanaraman A. An optimized noc architecture for accelerating TSP kernels in breakpoint median problem Proceedings of the International Conference On Application-Specific Systems, Architectures and Processors. 89-96. DOI: 10.1109/ASAP.2010.5540797  0.385
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