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Yao-Wen Chang, Ph.D. - Publications

Affiliations: 
Department of Electrical Engineering National Taiwan University, Taipei, Taipei City, Taiwan 
Area:
electronic design automation, combinatorial optimization
Website:
http://cc.ee.ntu.edu.tw/~ywchang/
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80 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Hsu C, Hung S, Chen H, Sun F, Chang Y. A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.3002546  0.349
2019 Su Y, Chang Y. DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 267-280. DOI: 10.1109/Tcad.2018.2812122  0.338
2018 Huang C, Lee H, Lin B, Yang S, Chang C, Chen S, Chang Y, Chen T, Bustany I. NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 669-681. DOI: 10.1109/Tcad.2017.2712665  0.409
2017 Lin Z, Chang Y. Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 2066-2079. DOI: 10.1109/Tcad.2017.2681281  0.424
2017 Su Y, Chang Y. Nanowire-Aware Routing Considering High Cut Mask Complexity Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 964-977. DOI: 10.1109/Tcad.2016.2614777  0.355
2016 Su Y, Huang Y, Tsai L, Chang Y, Banerjee S. Fast Lithographic Mask Optimization Considering Process Variation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1345-1357. DOI: 10.1109/Tcad.2015.2514082  0.338
2016 Liu IJ, Fang SY, Chang YW. Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1519-1531. DOI: 10.1109/Tcad.2015.2513670  0.39
2016 Ou H, Tseng K, Liu J, Wu I, Chang Y. Layout-Dependent Effects-Aware Analytical Analog Placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1243-1254. DOI: 10.1109/Tcad.2015.2501293  0.379
2016 Chiang HJK, Liu CY, Jiang JHR, Chang YW. Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummification Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 598-610. DOI: 10.1109/Tcad.2015.2488492  0.366
2015 Liu IJ, Fang SY, Chang YW. Stitch-aware routing for multiple e-beam lithography Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 471-482. DOI: 10.1109/Tcad.2014.2385761  0.317
2015 Ho K, Ou H, Chang Y, Tsao H. Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 161-172. DOI: 10.1109/Tcad.2014.2379656  0.397
2014 Ou H, Chien HC, Chang Y. Nonuniform Multilevel Analog Routing With Matching Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1942-1954. DOI: 10.1109/Tcad.2014.2363394  0.35
2014 Hsu M, Chen Y, Huang C, Chou S, Lin T, Chen T, Chang Y. NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1914-1927. DOI: 10.1109/Tcad.2014.2360453  0.369
2014 Fang S, Chang Y, Chen W. A Novel Layout Decomposition Algorithm for Triple Patterning Lithography Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 397-408. DOI: 10.1109/Tcad.2013.2288678  0.404
2014 Ho Y, Lee H, Lee W, Chang Y, Chang C, Lin I, Shen C. Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 224-236. DOI: 10.1109/Tcad.2013.2285275  0.45
2013 Chang H, Jiang IH, Chang Y. ECO Optimization Using Metal-Configurable Gate-Array Spare Cells Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1722-1733. DOI: 10.1109/Tcad.2013.2272540  0.358
2013 Ho Y, Lee H, Chang Y. Escape Routing for Staggered-Pin-Array PCBs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1347-1356. DOI: 10.1109/Tcad.2013.2259539  0.392
2013 Fang S, Chen W, Chang Y. Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 189-201. DOI: 10.1109/Tcad.2013.2237947  0.387
2013 Hsu M, Balabanov V, Chang Y. TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 497-509. DOI: 10.1109/Tcad.2012.2226584  0.369
2012 Chang H, Jiang IH, Chang Y. Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1857-1866. DOI: 10.1109/Tcad.2012.2209117  0.388
2012 Ho K, Jiang JR, Chang Y. TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1723-1733. DOI: 10.1109/Tcad.2012.2201480  0.34
2012 Hsu M, Chang Y. Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1366-1378. DOI: 10.1109/Tcad.2012.2193582  0.385
2012 Shih X, Chang Y. Fast Timing-Model Independent Buffered Clock-Tree Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1393-1404. DOI: 10.1109/Tcad.2012.2191554  0.372
2012 Lin C, Lee P, Chang Y, Shen C, Tseng W. An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 878-889. DOI: 10.1109/Tcad.2011.2181511  0.431
2012 Fang S, Chen S, Chang Y. Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 703-716. DOI: 10.1109/Tcad.2011.2179039  0.4
2011 Chuang Y, Lee P, Chang Y. Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1649-1662. DOI: 10.1109/Tcad.2011.2163071  0.355
2011 Lin CC, Chang Y. Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 817-828. DOI: 10.1109/Tcad.2011.2108010  0.382
2011 Hsu C, Chang Y, Nassif SR. Simultaneous Layout Migration and Decomposition for Double Patterning Technology Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 284-294. DOI: 10.1109/Tcad.2010.2079990  0.42
2010 Lin CC, Chang Y. ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1315-1327. DOI: 10.1109/Tcad.2010.2049157  0.396
2010 Fang J, Chang Y. Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 711-721. DOI: 10.1109/Tcad.2010.2043586  0.42
2010 Hsu C, Chen H, Chang Y. Multilayer Global Routing With Via and Wire Capacity Considerations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 685-696. DOI: 10.1109/Tcad.2010.2043575  0.386
2010 Ho K, Chen Y, Fang J, Chang Y. ECO Timing Optimization Using Spare Cells and Technology Remapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 697-710. DOI: 10.1109/Tcad.2010.2043573  0.374
2010 Chen T, Liao G, Chang Y. Predictive Formulae for OPC With Applications to Lithography-Friendly Routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 40-50. DOI: 10.1109/Tcad.2009.2032359  0.325
2009 Chang Y, Jiang Z, Chen T. Essential Issues in Analytical Placement Algorithms Ipsj Transactions On System Lsi Design Methodology. 2: 145-166. DOI: 10.2197/Ipsjtsldm.2.145  0.416
2009 Yuh P, Yang C, Chang Y. T-trees: A tree-based representation for temporal and three-dimensional floorplanning Acm Transactions On Design Automation of Electronic Systems. 14: 51. DOI: 10.1145/1562514.1562519  0.316
2009 Yuh P, Sapatnekar SS, Yang C, Chang Y. A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1295-1306. DOI: 10.1109/Tcad.2009.2023196  0.433
2009 Lin P, Chang Y, Lin S. Analog Placement Based on Symmetry-Island Formulation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 791-804. DOI: 10.1109/Tcad.2009.2017433  0.384
2009 Lee W, Liu H, Chang Y. Voltage-Island Partitioning and Floorplanning Under Timing Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 690-702. DOI: 10.1109/Tcad.2009.2013997  0.346
2009 Chen H, Chou S, Wang S, Chang Y. A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 193-206. DOI: 10.1109/Tcad.2008.2009156  0.373
2009 Fang J, Hsu C, Chang Y. An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 98-110. DOI: 10.1109/Tcad.2008.2009151  0.451
2008 Chen T, Yuh P, Chang Y, Huang F, Liu T. MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1621-1634. DOI: 10.1109/Tcad.2008.927760  0.418
2008 Jiang Z, Chang Y. An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1055-1065. DOI: 10.1109/Tcad.2008.923246  0.349
2008 Chen T, Jiang Z, Hsu T, Chen H, Chang Y. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1228-1240. DOI: 10.1109/Tcad.2008.923063  0.359
2008 Chen H, Chiang M, Chang Y, Chen L, Han B. Full-Chip Routing Considering Double-Via Insertion Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 844-857. DOI: 10.1109/Tcad.2008.917597  0.447
2008 Lin C, Chen S, Li C, Chang Y, Yang C. Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 643-653. DOI: 10.1109/Tcad.2008.917583  0.451
2008 Yuh P, Yang C, Chang Y. BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1928-1941. DOI: 10.1109/Tcad.2008.2006140  0.428
2008 Lin C, Huang S, Hsu K, Lee M, Chang Y. Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2007-2016. DOI: 10.1109/Tcad.2008.2006095  0.416
2008 Chen T, Chang Y, Lin S. A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 286-294. DOI: 10.1109/Tcad.2007.907065  0.389
2007 Yuh P, Yang C, Chang Y. Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation Acm Journal On Emerging Technologies in Computing Systems. 3: 13. DOI: 10.1145/1295231.1295234  0.36
2007 Yuh P, Yang C, Chang Y. Temporal floorplanning using the three-dimensional transitive closure subGraph Acm Transactions On Design Automation of Electronic Systems. 12: 37. DOI: 10.1145/1278349.1278350  0.339
2007 Su B, Chang Y. An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1818-1829. DOI: 10.1109/Tcad.2007.896307  0.419
2007 Li KS, Chang Y, Lee C, Su C, Chen JE. Multilevel Full-Chip Routing With Testability and Yield Enhancement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1625-1636. DOI: 10.1109/Tcad.2007.895587  0.39
2007 Su B, Chang Y, Hu J. An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 719-733. DOI: 10.1109/Tcad.2007.892338  0.398
2007 Liu C, Chang Y. Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 693-704. DOI: 10.1109/Tcad.2007.892336  0.342
2007 Lee H, Chang Y, Yang HH. MB $^{\ast}$ -Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1430-1444. DOI: 10.1109/Tcad.2007.891368  0.332
2007 Fang J, Lin I, Chang Y, Wang J. A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1417-1429. DOI: 10.1109/Tcad.2007.891364  0.434
2007 Chen T, Chang Y. Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1041-1053. DOI: 10.1109/Tcad.2006.884492  0.408
2006 Jiang IH, Pan S, Chang Y, Jou J. Reliable crosstalk-driven interconnect optimization Acm Transactions On Design Automation of Electronic Systems. 11: 88-103. DOI: 10.1145/1124713.1124720  0.392
2006 Li KS-, Su C, Chang Y, Lee C, Chen JE. IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2513-2525. DOI: 10.1109/Tcad.2006.881330  0.341
2006 Chen T, Chang Y. Modern floorplanning based on B/sup */-tree and fast simulated annealing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 637-650. DOI: 10.1109/Tcad.2006.870076  0.398
2006 Tu S, Chang Y, Jou J. RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2258-2264. DOI: 10.1109/Tcad.2005.860956  0.321
2006 Ho T, Chang Y, Chen S. Multilevel routing with jumper insertion for antenna avoidance Integration. 39: 420-432. DOI: 10.1016/J.Vlsi.2005.08.005  0.359
2005 Lin J, Chang Y. TCG: A transitive closure graph-based representation for general floorplans Ieee Transactions On Very Large Scale Integration Systems. 13: 288-292. DOI: 10.1109/Tvlsi.2004.840760  0.315
2005 Ho T, Chang Y, Chen S, Lee D. Crosstalk- and performance-driven multilevel full-chip routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 869-878. DOI: 10.1109/Tcad.2005.847902  0.4
2004 Chen T, Pan S, Chang Y. Timing modeling and optimization under the transmission line model Ieee Transactions On Very Large Scale Integration Systems. 12: 28-41. DOI: 10.1109/Tvlsi.2003.820529  0.359
2004 Jiang IH-, Chang Y, Jou J, Chao K. Simultaneous floor plan and buffer-block optimization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 694-703. DOI: 10.1109/Tcad.2004.826582  0.387
2004 Chang Y, Lin S. MR: a new framework for multilevel full-chip routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 793-800. DOI: 10.1109/Tcad.2004.826547  0.383
2004 Wu G, Chao MC, Chang Y. A clustering- and probability-based approach for time-multiplexed FPGA partitioning Integration. 38: 245-265. DOI: 10.1016/J.Vlsi.2004.06.003  0.356
2003 Wu G, Chang Y, Chang Y. Rectilinear block placement using B*-trees Acm Transactions On Design Automation of Electronic Systems. 8: 188-202. DOI: 10.1145/762488.762490  0.359
2003 Chang Y, Zhu K, Wu G, Wong DF, Wong CK. Analysis of FPGA/FPIC switch modules Acm Transactions On Design Automation of Electronic Systems. 8: 11-37. DOI: 10.1145/606603.606605  0.387
2003 Lin J, Chang Y, Lin S. Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme Ieee Transactions On Very Large Scale Integration Systems. 11: 679-686. DOI: 10.1109/Tvlsi.2003.816137  0.326
2002 Wu G, Lin J, Chang Y. Performance-driven placement for dynamically reconfigurable FPGAs Acm Transactions On Design Automation of Electronic Systems. 7: 628-642. DOI: 10.1145/605440.605447  0.371
2002 Lin J, Chen H, Chang Y. Arbitrarily shaped rectilinear module placement using the transitive closure graph representation Ieee Transactions On Very Large Scale Integration Systems. 10: 886-901. DOI: 10.1109/Tvlsi.2002.808431  0.365
2001 Wu G, Lin J, Chang Y. Generic ILP-based approaches for time-multiplexed FPGA partitioning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1266-1274. DOI: 10.1109/43.952745  0.39
2001 Chang Y, Lin J, Wong MDF. Matching-based algorithm for FPGA channel segmentation design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 784-791. DOI: 10.1109/43.924831  0.425
2000 Chang Y, Zhu K, Wong DF. Timing-driven routing for symmetrical array-based FPGAs Acm Transactions On Design Automation of Electronic Systems. 5: 433-450. DOI: 10.1145/348019.348101  0.416
2000 Jiang IH-, Chang Y, Jou J. Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 999-1010. DOI: 10.1109/43.863640  0.397
2000 Shyu M, Wu GM, Chang YD, Chang YW. Generic universal switch blocks Ieee Transactions On Computers. 49: 348-359. DOI: 10.1109/12.844347  0.309
1999 Wu G, Chang Y. Quasi-universal switch matrices for FPD design Ieee Transactions On Computers. 48: 1107-1122. DOI: 10.1109/12.805159  0.307
1997 Thakur S, Chang YW, Wong DF, Muthukrishnan S. Algorithms for an FPGA switch module routing problem with application to global routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 32-46. DOI: 10.1109/43.559330  0.424
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