Pramod Kumar Tiwari
Affiliations: | School of Studies in Zoology, Jiwaji Univ, Gwalior, India, Gwalior, Madhya Pradesh, India |
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"Pramod Tiwari"Parents
Sign in to add mentor| Subhash Chandra Lakhotia | grad student | 1979-1985 | Banaras Hindu UNiversity |
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Publications
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| Gola D, Singh B, Srinivas PSTN, et al. (2020) Thermal Noise Models for Trigate Junctionless Transistors Including Substrate Bias Effects Ieee Transactions On Electron Devices. 67: 263-269 |
| Kumar S, Singh Y, Singh B, et al. (2020) Simulation Study of Dielectric Modulated Dual Channel Trench Gate TFET Based Biosensor Ieee Sensors Journal. 1-1 |
| Srinivas PSTN, Kumar A, Jit S, et al. (2020) Self-heating effects and hot carrier degradation in In 0.53 Ga 0.47 As Gate-All-Around (GAA) MOSFETs Semiconductor Science and Technology. 35: 65008 |
| Moparthi S, Adarsh KP, Tiwari PK, et al. (2020) Analog and RF performance evaluation of negative capacitance SOI junctionless transistor Aeu-International Journal of Electronics and Communications. 122: 153243 |
| Duksh YS, Singh B, Gola D, et al. (2020) Subthreshold Modeling of Graded Channel Double Gate Junctionless FETs Silicon |
| Srinivas PSTN, Kumar A, Tiwari PK. (2020) Threshold Voltage Modeling of tri-Gate Schottky-Barrier (TGSB) Field-Effect-Transistors (FETs) Silicon. 1-11 |
| Purwar V, Gupta R, Kumar N, et al. (2020) Investigating linearity and effect of temperature variation on analog/RF performance of dielectric pocket high-k double gate-all-around (DP-DGAA) MOSFETs Applied Physics A. 126: 1-8 |
| Kumar A, Srinivas PSTN, Bhushan S, et al. (2019) Threshold Voltage Modeling of Double Gate-All-Around Metal-Oxide-Semiconductor Field-Effect-Transistors (DGAA MOSFETs) Including the Fringing Field Effects Journal of Nanoelectronics and Optoelectronics. 14: 1555-1564 |
| Gola D, Singh B, Tiwari PK. (2019) Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFET s Using Substrate Bias Induced Effects Ieee Transactions On Nanotechnology. 18: 329-335 |
| Gola D, Singh B, Singh J, et al. (2019) Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor With Substrate Bias-Induced Effects Ieee Transactions On Electron Devices. 66: 2876-2883 |