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Bendik Kleveland, Ph.D. - Publications

Affiliations: 
2000 Stanford University, Palo Alto, CA 
Area:
Electronics and Electrical Engineering
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9 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Vamvakos SD, Gauthier CR, Rao C, Wang A, Canagasaby KR, Abugharbieh K, Choudhary P, Dabral S, Desai S, Hassan M, Hsieh KC, Kleveland B, Mandal G, Rouse R, Saraf R, et al. A 2.488-11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications Analog Integrated Circuits and Signal Processing. 78: 259-273. DOI: 10.1007/S10470-013-0172-1  0.345
2012 Vamvakos SD, Gauthier CR, Rao C, Canagasaby KR, Choudhary P, Dabral S, Desai S, Hassan M, Hsieh KC, Kleveland B, Mandal G, Rouse R, Saraf R, Wang A, Yeung J, et al. A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications Midwest Symposium On Circuits and Systems. 5-8. DOI: 10.1109/MWSCAS.2012.6291943  0.365
2003 Johnson M, Al-Shamma A, Bosch D, Crowley M, Farmwald M, Fasoli L, Ilkbahar A, Kleveland B, Lee T, Liu TY, Nguyen Q, Scheuerlein R, So K, Thorp T. 512-Mb PROM with a three-dimensional array of diode/antifuse memory cells Ieee Journal of Solid-State Circuits. 38: 1920-1928. DOI: 10.1109/Jssc.2003.818147  0.318
2003 Wong SS, Yue P, Chang R, Kim SY, Kleveland B, O'Mahony F. On-chip interconnect inductance - friend or foe Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 389-394. DOI: 10.1109/ISQED.2003.1194764  0.355
2002 Kleveland B, Diaz CH, Vook D, Madden L, Lee TH, Wong SS. Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design" Ieee Journal of Solid-State Circuits. 37: 255-255. DOI: 10.1109/Jssc.2002.982433  0.373
2002 Kleveland B, Qi X, Madden L, Furusawa T, Dutton RW, Horowitz MA, Simon Wong S. High-frequency characterization of on-chip digital interconnects Ieee Journal of Solid-State Circuits. 37: 716-725. DOI: 10.1109/Jssc.2002.1004576  0.379
2001 Kleveland B, Diaz CH, Vook D, Madden L, Lee TH, Wong SS. Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design Ieee Journal of Solid-State Circuits. 36: 1480-1488. DOI: 10.1109/4.953476  0.449
2000 Kleveland B, Maloney TJ, Morgan I, Madden L, Lee TH, Wong SS. Distributed ESD protection for high-speed integrated circuits Ieee Electron Device Letters. 21: 390-392. DOI: 10.1109/55.852960  0.369
2000 Qi X, Kleveland B, Yu Z, Wong S, Dutton R, Young T. On-chip inductance modeling of VLSI interconnects Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 172-173.  0.414
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