Year |
Citation |
Score |
2020 |
Kim B, Abraham JA. Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters Ieee Access. 8: 7851-7860. DOI: 10.1109/Access.2020.2964632 |
0.399 |
|
2019 |
Kim B, Abraham JA. Spectral Leakage-Driven Loopback Scheme for Prediction of Mixed-Signal Circuit Specifications Ieee Transactions On Industrial Electronics. 66: 586-594. DOI: 10.1109/Tie.2018.2829667 |
0.372 |
|
2019 |
Banerjee S, Samynathan B, Abraham J, Chatterjee A. Real-Time Error Detection in Nonlinear Control Systems Using Machine Learning Assisted State-Space Encoding Ieee Transactions On Dependable and Secure Computing. 1-1. DOI: 10.1109/Tdsc.2019.2903049 |
0.592 |
|
2018 |
Cheng E, Mirkhani S, Szafaryn LG, Cher C, Cho H, Skadron K, Stan MR, Lilja K, Abraham JA, Bose P, Mitra S. Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1839-1852. DOI: 10.1109/Tcad.2017.2752705 |
0.39 |
|
2017 |
Fang J, Thirunakkarasu S, Yu X, Silva-Rivas F, Zhang C, Singor F, Abraham J. A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS Ieee Transactions On Circuits and Systems. 64: 1673-1683. DOI: 10.1109/Tcsi.2017.2661481 |
0.349 |
|
2017 |
Zahir Z, Banerjee G, Zeidan MA, Abraham JA. A multi-band low noise amplifier with strong immunity to interferers Analog Integrated Circuits and Signal Processing. 93: 13-27. DOI: 10.1007/S10470-017-1020-5 |
0.31 |
|
2015 |
Jang EJ, Chung J, Abraham JA. Delay defect diagnosis methodology using path delay measurements Ieice Transactions On Electronics. 991-994. DOI: 10.1587/Transele.E98.C.991 |
0.358 |
|
2015 |
Raja I, Banerjee G, Zeidan MA, Abraham JA. A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2478804 |
0.358 |
|
2015 |
Lee HC, Abraham JA. Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction Journal of Electronic Testing: Theory and Applications (Jetta). 31: 127-138. DOI: 10.1007/S10836-015-5516-6 |
0.355 |
|
2014 |
Mirkhani S, Abraham JA. Fast evaluation of test vector sets using a simulation-based statistical metric Proceedings of the Ieee Vlsi Test Symposium. DOI: 10.1109/VTS.2014.6818739 |
0.34 |
|
2014 |
Kim B, Abraham JA. Bitstream-driven built-in characterization for analog and mixed-signal embedded circuits Ieee Transactions On Circuits and Systems Ii: Express Briefs. 61: 743-747. DOI: 10.1109/Tcsii.2014.2335436 |
0.37 |
|
2014 |
Kim B, Abraham JA. Dynamic performance characterization of embedded single-ended mixed-signal circuits Ieee Transactions On Circuits and Systems Ii: Express Briefs. 61: 329-333. DOI: 10.1109/Tcsii.2014.2312639 |
0.433 |
|
2014 |
Kim B, Abraham JA. Designing nonlinearity characterization for mixed-signal circuits in system-on-chip Analog Integrated Circuits and Signal Processing. 82: 341-348. DOI: 10.1007/S10470-014-0461-3 |
0.386 |
|
2013 |
Chung J, Abraham JA. Concurrent path selection algorithm in statistical timing analysis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1715-1726. DOI: 10.1109/Tvlsi.2012.2218136 |
0.409 |
|
2013 |
Chung J, Park J, Abraham JA. A built-in repair analyzer with optimal repair rate for word-oriented memories Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 281-291. DOI: 10.1109/Tvlsi.2011.2182217 |
0.421 |
|
2013 |
Prabhu M, Abraham JA. Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults Proceedings - International Test Conference. DOI: 10.1109/TEST.2013.6651915 |
0.372 |
|
2013 |
Kim B, Abraham JA. Capacitor-coupled built-off self-test in analog and mixed-signal embedded systems Ieee Transactions On Circuits and Systems Ii: Express Briefs. 60: 257-261. DOI: 10.1109/Tcsii.2013.2251953 |
0.389 |
|
2013 |
Park J, Chaudhari A, Abraham JA. Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor Proceedings -Design, Automation and Test in Europe, Date. 254-257. |
0.334 |
|
2012 |
Viswanath V, Abraham JA. Automatic and correct register transfer level annotations for low power microprocessor design Journal of Low Power Electronics. 8: 424-439. DOI: 10.1166/Jolpe.2012.1204 |
0.391 |
|
2012 |
Pu X, Nagaraj K, Abraham JA, Thomsen A. A novel fractional-N PLL based on a simple reference multiplier Journal of Circuits, Systems, and Computers. 21: 1240010. DOI: 10.1142/S0218126612400105 |
0.337 |
|
2012 |
Kim B, Abraham JA. Imbalance-based self-test for high-speed mixed-signal embedded systems Ieee Transactions On Circuits and Systems Ii: Express Briefs. 59: 785-789. DOI: 10.1109/Tcsii.2012.2220693 |
0.368 |
|
2012 |
Zeidan MA, Banerjee G, Gharpurey R, Abraham JA. Phase-aware multitone digital signal based test for RF receivers Ieee Transactions On Circuits and Systems I: Regular Papers. 59: 2097-2110. DOI: 10.1109/Tcsi.2012.2185309 |
0.383 |
|
2012 |
Chung J, Abraham JA. On computing criticality in refactored timing graphs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1935-1939. DOI: 10.1109/Tcad.2012.2213819 |
0.363 |
|
2012 |
Chung J, Xiong J, Zolotov V, Abraham JA. Testability-driven statistical path selection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1275-1287. DOI: 10.1109/Tcad.2012.2190067 |
0.356 |
|
2012 |
Chung J, Xiong J, Zolotov V, Abraham JA. Path criticality computation in parameterized statistical timing analysis using a novel operator Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 497-508. DOI: 10.1109/Tcad.2011.2179042 |
0.324 |
|
2012 |
Chung J, Abraham JA. Refactoring of timing graphs and its use in capturing topological correlation in SSTA Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 485-496. DOI: 10.1109/Tcad.2011.2176731 |
0.394 |
|
2012 |
Prabhu M, Abraham JA. Functional test generation for hard to detect stuck-at faults using RTL model checking Proceedings - 2012 17th Ieee European Test Symposium, Ets 2012. DOI: 10.1109/ETS.2012.6233016 |
0.306 |
|
2012 |
Mohammad B, Abraham J. A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory Microelectronics Journal. 43: 110-118. DOI: 10.1016/J.Mejo.2011.11.006 |
0.648 |
|
2012 |
Dasnurkar SD, Abraham JA. Calibration enabled scalable current Sensor module for quiescent current testing Journal of Electronic Testing: Theory and Applications (Jetta). 28: 697-704. DOI: 10.1007/S10836-012-5327-Y |
0.421 |
|
2012 |
Kim HJ, Abraham JA. A Built-In Self-Test scheme for memory interfaces timing Test and measurement Journal of Electronic Testing: Theory and Applications (Jetta). 28: 585-597. DOI: 10.1007/S10836-012-5324-1 |
0.358 |
|
2012 |
Zhang C, Gharpurey R, Abraham JA. Built-in self test of RF subsystems with integrated detectors Journal of Electronic Testing: Theory and Applications (Jetta). 28: 557-569. DOI: 10.1007/S10836-012-5315-2 |
0.61 |
|
2011 |
Kim B, Abraham JA. Transformer-coupled loopback test for differential mixed-signal dynamic specifications Ieee Transactions On Instrumentation and Measurement. 60: 2014-2024. DOI: 10.1109/Tim.2011.2113128 |
0.409 |
|
2011 |
Kim B, Abraham JA. Efficient loopback test for aperture jitter in embedded mixed-signal circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1773-1784. DOI: 10.1109/Tcsi.2011.2106030 |
0.386 |
|
2011 |
Vemu R, Abraham J. CEDA: Control-flow error detection using assertions Ieee Transactions On Computers. 60: 1233-1245. DOI: 10.1109/Tc.2011.101 |
0.784 |
|
2011 |
Park J, Shin H, Abraham JA. Pseudorandom test of nonlinear analog and mixed-signal circuits based on a volterra series model Journal of Electronic Testing: Theory and Applications (Jetta). 27: 321-334. DOI: 10.1007/S10836-011-5227-6 |
0.389 |
|
2011 |
Han K, Park J, Lee JW, Chung J, Byun E, Woo CJ, Oh S, Abraham JA. Off-chip Skew Measurement and Compensation Module (SMCM) design for built-off test chip Journal of Electronic Testing: Theory and Applications (Jetta). 27: 429-439. DOI: 10.1007/S10836-011-5213-Z |
0.439 |
|
2010 |
Chung J, Park J, Abraham JA, Byun E, Woo CJ. Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate Proceedings of the Ieee Vlsi Test Symposium. 33-38. DOI: 10.1109/VTS.2010.5469625 |
0.337 |
|
2010 |
Dasnurkar SD, Abraham JA. Calibration-enabled scalable built-in current sensor compatible with Very Low Cost ATE 2010 15th Ieee European Test Symposium, Ets'10. 119-124. DOI: 10.1109/ETSYM.2010.5512770 |
0.343 |
|
2010 |
Datta R, Sebastine A, Raghunathan A, Carpenter G, Nowka K, Abraham JA. On-chip delay measurement based response analysis for timing characterization Journal of Electronic Testing: Theory and Applications (Jetta). 26: 599-619. DOI: 10.1007/S10836-010-5188-1 |
0.572 |
|
2010 |
Shin H, Park J, Abraham JA. Spectral prediction for specification-based loopback test of embedded mixed-signal circuits Journal of Electronic Testing: Theory and Applications (Jetta). 26: 73-86. DOI: 10.1007/S10836-009-5136-0 |
0.563 |
|
2009 |
Viswanath V, Vasudevan S, Abraham JA. Dedicated rewriting: Automatic verification of low power transformations in Register Transfer Level Journal of Low Power Electronics. 5: 339-353. DOI: 10.1166/Jolpe.2009.1034 |
0.58 |
|
2009 |
Sundareswaran S, Abraham JA, Panda R, Ardelea A. Characterization of standard cells for intra-cell mismatch variations Ieee Transactions On Semiconductor Manufacturing. 22: 40-49. DOI: 10.1109/Tsm.2008.2011666 |
0.656 |
|
2009 |
Sambamurthy S, Gurumurthy S, Vemu R, Abraham JA. Functionally valid gate-level peak power estimation for processors Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 753-758. DOI: 10.1109/ISQED.2009.4810387 |
0.747 |
|
2009 |
Sundareswaran S, Abraham JA, Panda R, Zhang Y, Mittal A. Characterization of Sequential Cells for Constraint Sensitivities Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 74-79. DOI: 10.1109/ISQED.2009.4810272 |
0.649 |
|
2009 |
Park J, Madhavapeddi S, Paglieri A, Barr C, Abraham JA. Defect-based analog fault coverage analysis using mixed-mode fault simulation 2009 Ieee 15th International Mixed-Signals, Sensors, and Systems Test Workshop, Ims3tw '09. DOI: 10.1109/IMS3TW.2009.5158688 |
0.301 |
|
2009 |
Han K, Park J, Lee JW, Abraham JA, Byun E, Woo CJ, Oh S. Low-complexity off-chip skew measurement and compensation module (SMCM) design for built-off test chip Proceedings of the 14th Ieee European Test Symposium, Ets 2009. 129-134. DOI: 10.1109/ETS.2009.20 |
0.343 |
|
2009 |
Park J, Chung J, Abraham JA. LFSR-based performance characterization of nonlinear analog and mixed-signal circuits Proceedings of the Asian Test Symposium. 373-378. DOI: 10.1109/ATS.2009.66 |
0.302 |
|
2009 |
Tayade R, Abraham JA. Critical path selection for delay test considering coupling noise Proceedings of the 14th Ieee European Test Symposium, Ets 2009. 163-168. DOI: 10.1007/S10836-009-5105-7 |
0.739 |
|
2008 |
Gurumurthy S, Vemu R, Abraham JA, Natarajan S. On efficient generation of instruction sequences to test for delay defects in a processor Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 279-284. DOI: 10.1145/1366110.1366178 |
0.781 |
|
2008 |
Dou Q, Abraham JA. Low-cost test of timing mismatch among time-interleaved A/D converters in high-speed communication systems Proceedings of the Ieee Vlsi Test Symposium. 3-8. DOI: 10.1109/VTS.2008.57 |
0.51 |
|
2008 |
Park J, Shin H, Abraham JA. Parallel loopback test of mixed-signal circuits Proceedings of the Ieee Vlsi Test Symposium. 309-316. DOI: 10.1109/VTS.2008.53 |
0.332 |
|
2008 |
Sambamurthy S, Abraham JA, Tupuri RS. A robust top-down dynamic power estimation methodology for delay constrained register transfer level sequential circuits Proceedings of the Ieee International Frequency Control Symposium and Exposition. 521-526. DOI: 10.1109/VLSI.2008.56 |
0.311 |
|
2008 |
Vemu R, Gurumurthy S, Abraham JA. ACCE: Automatic correction of control-flow errors Proceedings - International Test Conference. DOI: 10.1109/TEST.2007.4437639 |
0.768 |
|
2008 |
Sundareswaran S, Nechanicka L, Panda R, Gavrilov S, Solovyev R, Abraham JA. A timing methodology considering within-die clock skew variations 2008 Ieee International Soc Conference, Socc. 351-356. DOI: 10.1109/SOCC.2008.4641543 |
0.667 |
|
2008 |
Yang Y, Sculley T, Abraham J. A Single-Die 124 dB Stereo Audio Delta-Sigma ADC With 111 dB THD Ieee Journal of Solid-State Circuits. 43: 1657-1665. DOI: 10.1109/Jssc.2008.923731 |
0.376 |
|
2008 |
Vemu R, Abraham JA. Budget-dependent control-flow error detection Proceedings - 14th Ieee International On-Line Testing Symposium, Iolts 2008. 73-78. DOI: 10.1109/IOLTS.2008.52 |
0.797 |
|
2008 |
Dou Q, Abraham JA. Jitter decomposition in high-speed communication systems Proceedings - 13th Ieee European Test Symposium, Ets 2008. 157-162. DOI: 10.1109/ETS.2008.35 |
0.518 |
|
2008 |
Vemu R, Jas A, Abraham JA, Patil S, Galivanche R. A low-cost concurrent error detection technique for processor control logic Proceedings -Design, Automation and Test in Europe, Date. 897-902. DOI: 10.1109/DATE.2008.4484788 |
0.796 |
|
2008 |
Tayade R, Abraham J. Small-delay defect detection in the presence of process variations Microelectronics Journal. 39: 1093-1100. DOI: 10.1016/J.Mejo.2008.01.003 |
0.757 |
|
2008 |
Datta R, Gupta R, Sebastine A, Abraham JA, D'Abreu M. Controllability of static CMOS circuits for timing characterization Journal of Electronic Testing: Theory and Applications (Jetta). 24: 481-496. DOI: 10.1007/S10836-007-5059-6 |
0.612 |
|
2008 |
Datta R, Abraham JA, Utku Diril A, Chatterjee A, Nowka KJ. Performance-optimized design for parametric reliability Journal of Electronic Testing: Theory and Applications (Jetta). 24: 129-141. DOI: 10.1007/S10836-007-5001-Y |
0.624 |
|
2008 |
Vasudevan S, Viswanath V, Abraham JA, Tu J. Sequential equivalence checking between system level and RTL descriptions Design Automation For Embedded Systems. 12: 377-396. DOI: 10.1007/S10617-008-9033-Z |
0.598 |
|
2007 |
Vasudevan S, Viswanath V, Sumners RW, Abraham JA. Automatic verification of arithmetic circuits in RTL using stepwise refinement of term rewriting systems Ieee Transactions On Computers. 56: 1401-1414. DOI: 10.1109/Tc.2007.1073 |
0.721 |
|
2007 |
Vasudevan S, Emerson EA, Abraham JA. Improved verification of hardware designs through antecedent conditioned slicing International Journal On Software Tools For Technology Transfer. 9: 89-101. DOI: 10.1007/S10009-006-0022-X |
0.579 |
|
2005 |
Vasudevan S, Emerson EA, Abraham JA. Efficient model checking of hardware using conditioned slicing Electronic Notes in Theoretical Computer Science. 128: 279-294. DOI: 10.1016/J.Entcs.2005.04.017 |
0.564 |
|
2004 |
Roh J, Abraham JA. Subband Filtering for Time and Frequency Analysis of Mixed-Signal Circuit Testing Ieee Transactions On Instrumentation and Measurement. 53: 602-611. DOI: 10.1109/Tim.2003.820494 |
0.502 |
|
2003 |
Hwang S, Abraham JA. Test data compression and test time reduction using an embedded microprocessor Ieee Transactions On Very Large Scale Integration Systems. 11: 853-862. DOI: 10.1109/Tvlsi.2003.817140 |
0.411 |
|
2003 |
Roh J, Abraham JA. A comprehensive signature analysis scheme for oscillation-test Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1409-1423. DOI: 10.1109/Tcad.2003.818133 |
0.541 |
|
2003 |
Vedula VM, Abraham JA, Bhadra J, Tupuri R. A hierarchical test generation approach using program slicing techniques on hardware description languages Journal of Electronic Testing: Theory and Applications (Jetta). 19: 149-160. DOI: 10.1023/A:1022885523034 |
0.789 |
|
2001 |
Krishnamurthy N, Abadir MS, Martin AK, Abraham JA. Design and development paradigm for industrial formal verification CAD tools Ieee Design & Test of Computers. 18: 26-35. DOI: 10.1109/54.936246 |
0.383 |
|
2001 |
Seshadri S, Abraham JA. Frequency Response Verification of Analog Circuits Using Global Optimization Techniques Journal of Electronic Testing. 17: 395-408. DOI: 10.1023/A:1012751118746 |
0.38 |
|
2001 |
Bhadra J, Martin A, Abraham JA, Abadir MS. Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation Lecture Notes in Computer Science. 386-402. DOI: 10.1007/3-540-44798-9_30 |
0.619 |
|
2000 |
Krishnamurthy N, Martin AK, Abadir MS, Abraham JA. Validating PowerPC microprocessor custom memories Ieee Design & Test of Computers. 17: 61-76. DOI: 10.1109/54.895007 |
0.4 |
|
1999 |
Alkhalifa Z, Nair VSS, Krishnamurthy N, Abraham JA. Design and evaluation of system-level checks for on-line control flow error detection Ieee Transactions On Parallel and Distributed Systems. 10: 627-641. DOI: 10.1109/71.774911 |
0.433 |
|
1999 |
Mukherjee R, Jain J, Takayama K, Fujita M, Abraham JA, Fussell DS. An efficient filter-based approach for combinational verification Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1542-1557. DOI: 10.1109/43.806801 |
0.458 |
|
1998 |
Nagi N, Chatterjee A, Yoon H, Abraham JA. Signature analysis for analog and mixed-signal circuit test response compaction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 540-546. DOI: 10.1109/43.703834 |
0.376 |
|
1998 |
Moundanos D, Abraham JA, Hoskote YV. Abstraction techniques for validation coverage analysis and test generation Ieee Transactions On Computers. 47: 2-14. DOI: 10.1109/12.656068 |
0.474 |
|
1998 |
Shen J, Abraham JA. Synthesis of Native Mode Self-Test Programs Journal of Electronic Testing. 13: 137-148. DOI: 10.1023/A:1008305820979 |
0.443 |
|
1997 |
Jain J, Bitner J, Abadir MS, Abraham JA, Fussell DS. Indexed BDDs: Algorithmic advances in techniques to represent and verify Boolean functions Ieee Transactions On Computers. 46: 1230-1245. DOI: 10.1109/12.644298 |
0.355 |
|
1996 |
Balivada A, Chen J, Abraham J. Analog testing with time response parameters Ieee Design & Test of Computers. 13: 18-25. DOI: 10.1109/54.500197 |
0.424 |
|
1996 |
Saab DG, Saab YG, Abraham JA. Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1278-1285. DOI: 10.1109/43.541447 |
0.48 |
|
1996 |
Nair VSS, Abraham JA, Banerjee P. Efficient techniques for the analysis of algorithm-based fault tolerance (ABFT) schemes Ieee Transactions On Computers. 45: 499-503. DOI: 10.1109/12.494110 |
0.397 |
|
1996 |
Nagi N, Abraham JA. Hierarchical fault modeling for linear analog circuits Analog Integrated Circuits and Signal Processing. 10: 89-99. DOI: 10.1007/Bf00713981 |
0.393 |
|
1996 |
Balivada A, Zheng H, Nagi N, Chatterjee A, Abraham JA. A unified approach for fault simulation of linear mixed-signal circuits Journal of Electronic Testing. 9: 29-41. DOI: 10.1007/Bf00137563 |
0.575 |
|
1995 |
Kanawati GA, Kanawati NA, Abraham JA. FERRARI: a flexible software-based fault and error injection system Ieee Transactions On Computers. 44: 248-260. DOI: 10.1109/12.364536 |
0.421 |
|
1994 |
Levitt ME, Roy K, Abraham JA. BiCMOS logic testing Ieee Transactions On Very Large Scale Integration Systems. 2: 241-248. DOI: 10.1109/92.285749 |
0.47 |
|
1994 |
Chang H, Abraham JA. An efficient critical path tracing algorithm for sequential circuits Microprocessing and Microprogramming. 40: 913-916. DOI: 10.1016/0165-6074(94)90068-X |
0.406 |
|
1993 |
Narain P, Saab DG, Kunda RP, Abraham JA. A High-Level Approach to Test Generation Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 40: 483-492. DOI: 10.1109/81.257304 |
0.365 |
|
1993 |
Mueller-Thuns RB, Saab DG, Damianc RF, Abraham JA. Benchmarking Parallel Processing Platforms: An Applications Perspective Ieee Transactions On Parallel and Distributed Systems. 4: 947-954. DOI: 10.1109/71.238628 |
0.349 |
|
1993 |
Mueller-Thuns RB, Saab DG, Damiano RF, Abraham JA. VLSI Logic and Fault Simulation on General-Purpose Parallel Computers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 12: 446-460. DOI: 10.1109/43.215006 |
0.425 |
|
1993 |
Nagi N, Chatterjee A, Abraham JA. Fault simulation of linear analog circuits Journal of Electronic Testing. 4: 345-360. DOI: 10.1007/Bf00972159 |
0.569 |
|
1992 |
Niermann TM, Roy RK, Patel JH, Abraham JA. Test Compaction for Sequential Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 11: 260-267. DOI: 10.1109/43.124404 |
0.449 |
|
1992 |
Nair VSS, Hoskote YV, Abraham JA. Probabilistic evaluation of online checks in fault-tolerant multiprocessor systems Ieee Transactions On Computers. 41: 532-541. DOI: 10.1109/12.142679 |
0.387 |
|
1992 |
Chen C, Abraham JA. Generation and evaluation of current and logic tests for switch-level sequential circuits Journal of Electronic Testing. 3: 359-366. DOI: 10.1007/Bf00135339 |
0.432 |
|
1991 |
Chatterjee A, Roy RK, Abraham JA, Patel JH. Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors Digital Signal Processing. 1: 231-244. DOI: 10.1016/1051-2004(91)90115-2 |
0.432 |
|
1991 |
Chatterjee A, Abraham JA. Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling Journal of Electronic Testing. 2: 351-372. DOI: 10.1007/Bf00135230 |
0.369 |
|
1990 |
Levitt ME, Abraham JA. Physical design of testable VLSI: techniques and experiments Ieee Journal of Solid-State Circuits. 25: 474-481. DOI: 10.1109/4.52172 |
0.491 |
|
1990 |
Mazumder P, Patel JH, Abraham JA. A Reconfigurable Parallel Signature Analyzer for Concurrent Error Correction in DRAM Ieee Journal of Solid-State Circuits. 25: 866-870. DOI: 10.1109/4.102687 |
0.391 |
|
1990 |
Banerjee P, Rahmeh JT, Stunkel C, Nair VS, Roy K, Balasubramanian V, Abraham JA. Algorithm-based fault tolerance on a hypercube multiprocessor Ieee Transactions On Computers. 39: 1132-1145. DOI: 10.1109/12.57055 |
0.407 |
|
1990 |
Nair VSS, Abraham JA. Real-number codes for fault-tolerant matrix operations on processor arrays Ieee Transactions On Computers. 39: 426-435. DOI: 10.1109/12.54836 |
0.327 |
|
1990 |
Saab DG, Mueller-Thuns RB, Blaauw D, Rahmeh JT, Abraham JA. Hierarchical multi-level fault simulation of large systems Journal of Electronic Testing. 1: 139-149. DOI: 10.1007/Bf00137390 |
0.395 |
|
1988 |
Jou J-, Abraham JA. Fault-tolerant FFT networks Ieee Transactions On Computers. 37: 548-561. DOI: 10.1109/12.4606 |
0.4 |
|
1987 |
Rogers WA, Guzolek JF, Abraham JA. Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 848-862. DOI: 10.1109/Tcad.1987.1270328 |
0.408 |
|
1987 |
Chatterjee A, Abraham JA. On the C-Testability of Generalized Counters Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 6: 713-726. DOI: 10.1109/Tcad.1987.1270317 |
0.427 |
|
1987 |
Fuchs WK, Chen C-R, Abraham JA. Concurrent error detection in highly structured logic arrays Ieee Journal of Solid-State Circuits. 22: 583-594. DOI: 10.1109/Jssc.1987.1052776 |
0.418 |
|
1986 |
Shih H, Rahmeh JT, Abraham JA. FAUST: An MOS Fault Simulator with Timing Information Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 5: 557-563. DOI: 10.1109/Tcad.1986.1270226 |
0.406 |
|
1985 |
Jha NK, Abraham JA. Design of Testable CMOS Logic Circuits Under Arbitrary Delays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 4: 264-269. DOI: 10.1109/Tcad.1985.1270122 |
0.468 |
|
1984 |
Banerjee P, Abraham JA. Characterization and Testing of Physical Failures in MOS Logic Circuits Ieee Design & Test of Computers. 1: 76-86. DOI: 10.1109/Mdt.1984.5005655 |
0.447 |
|
1983 |
Abraham JA, Davidson ES, Patel JH. Memory system design for tolerating single event upsets Ieee Transactions On Nuclear Science. 30: 4339-4344. DOI: 10.1109/Tns.1983.4333134 |
0.398 |
|
1982 |
Chou TCK, Abraham JA. Load Balancing in Distributed Systems Ieee Transactions On Software Engineering. 8: 401-412. DOI: 10.1109/Tse.1982.235574 |
0.309 |
|
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