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Jayanta Bhadra, Ph.D. - Publications

Affiliations: 
2001 University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Electronics and Electrical Engineering
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21 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2017 Chen W, Ray S, Bhadra J, Abadir M, Wang L. Challenges and Trends in Modern SoC Design Verification Ieee Design & Test of Computers. 34: 7-22. DOI: 10.1109/Mdat.2017.2735383  0.322
2017 Abadir M, Bhadra J, Chen W, Wang L. Guest Editors’ Introduction: Emerging Challenges and Solutions in SoC Verification Ieee Design & Test of Computers. 34: 5-6. DOI: 10.1109/Mdat.2017.2729938  0.361
2017 Chen W, Hsieh K, Wang L, Bhadra J. Data-Driven Test Plan Augmentation for Platform Verification Ieee Design & Test of Computers. 34: 23-29. DOI: 10.1109/Mdat.2017.2713390  0.373
2013 Ray S, Bhadra J, Abadir MS, Wang LC. Guest Editorial: Test and verification challenges for future microprocessors and SoC designs Journal of Electronic Testing: Theory and Applications (Jetta). 29: 621-623. DOI: 10.1007/S10836-013-5411-Y  0.423
2012 Chang CL, Chang CC, Chan HL, Wen CHP, Bhadra J. An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 163-168. DOI: 10.1109/ASPDAC.2012.6164938  0.313
2010 Chang PH, Wang LC, Bhadra J. A kernel-based approach for functional test program generation Proceedings - International Test Conference. DOI: 10.1109/TEST.2010.5699216  0.512
2009 Abadir MS, Bhadra J, Wang LC. Proceedings - International Workshop on Microprocessor Test and Verification: Preface Proceedings - International Workshop On Microprocessor Test and Verification. DOI: 10.1109/MTV.2009.4  0.374
2009 Bose M, Naphade P, Bhadra J, Miller H. An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 377-381. DOI: 10.1109/ISQED.2009.4810324  0.316
2008 Bhadra J, Trofimova E, Abadir MS. Validating power architecture technology-based MPSoCs through executable specifications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 388-396. DOI: 10.1109/Tvlsi.2008.917418  0.338
2008 Guzey O, Wang LC, Bhadra J. Enhancing signal controllability in functional test-benches through automatic constraint extraction Proceedings - International Test Conference. DOI: 10.1109/TEST.2007.4437615  0.386
2008 Abadir MS, Wang LC, Bhadra J. Proceedings - International Workshop on Microprocessor Test and Verification: Preface: MTV 2007 Proceedings - International Workshop On Microprocessor Test and Verification. DOI: 10.1109/MTV.2007.26  0.374
2007 Koo HM, Mishra P, Bhadra J, Abadir M. Directed micro-architectural test generation for an industrial processor: A case study Proceedings - International Workshop On Microprocessor Test and Verification. 33-36. DOI: 10.1109/MTV.2006.10  0.501
2007 Bhadra J, Abadir MS, Wang LC. Guest editors' introduction: Attacking functional verification through hybrid techniques Ieee Design and Test of Computers. 24: 110-111. DOI: 10.1109/Mdt.2007.45  0.3
2007 Bhadra J, Abadir MS, Wang LC, Ray S. A survey of hybrid techniques for functional verification Ieee Design and Test of Computers. 24: 112-122. DOI: 10.1109/Mdt.2007.30  0.399
2006 Bhadra J. Theory and practice of automatic design constraint generation Iee Proceedings: Computers and Digital Techniques. 153: 9-19. DOI: 10.1049/ip-cdt:20050114  0.391
2004 Bhadra J, Krishnamurthy N, Abadir MS. Enhanced equivalence checking: Toward a solidarity of functional verification and manufacturing test generation Ieee Design and Test of Computers. 21: 494-502. DOI: 10.1109/Mdt.2004.87  0.497
2003 Vedula VM, Abraham JA, Bhadra J, Tupuri R. A hierarchical test generation approach using program slicing techniques on hardware description languages Journal of Electronic Testing: Theory and Applications (Jetta). 19: 149-160. DOI: 10.1023/A:1022885523034  0.559
2002 Vedula VM, Abraham JA, Bhadra J. Program slicing for hierarchical test generation Proceedings of the Ieee Vlsi Test Symposium. 2002: 237-243. DOI: 10.1109/VTS.2002.1011144  0.602
2002 Bhadra J, Krishnamurthy N. Automatic generation of design constraints in verifying high performance embedded dynamic circuits Ieee International Test Conference (Tc). 213-222.  0.565
2001 Zeng J, Abadir MS, Bhadra J, Abraham JA. Full chip false timing path identification: Applications to the PowerPCTM microprocessors Proceedings -Design, Automation and Test in Europe, Date. 514-518. DOI: 10.1109/DATE.2001.915072  0.3
2001 Bhadra J, Martin A, Abraham JA, Abadir MS. Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation Lecture Notes in Computer Science. 386-402. DOI: 10.1007/3-540-44798-9_30  0.476
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