Year |
Citation |
Score |
2020 |
Shylendra A, Shukla P, Mukhopadhyay S, Bhunia S, Trivedi AR. Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics Ieee Transactions On Very Large Scale Integration Systems. 28: 1833-1843. DOI: 10.1109/Tvlsi.2020.2984472 |
0.533 |
|
2020 |
Deb Nath AP, Boddupalli S, Bhunia S, Ray S. Resilient System-on-Chip Designs With NoC Fabrics Ieee Transactions On Information Forensics and Security. 15: 2808-2823. DOI: 10.1109/Tifs.2020.2977534 |
0.369 |
|
2020 |
Roy I, Rebeiro C, Hazra A, Bhunia S. SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 752-765. DOI: 10.1109/Tcad.2019.2897629 |
0.369 |
|
2020 |
Hoque T, Chakraborty RS, Bhunia S. Hardware Obfuscation and Logic Locking: A Tutorial Introduction Ieee Design & Test. 37: 59-77. DOI: 10.1109/Mdat.2020.2984224 |
0.404 |
|
2019 |
Shylendra A, Bhunia S, Trivedi AR. An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 1253-1261. DOI: 10.1109/Tvlsi.2019.2903807 |
0.405 |
|
2018 |
Huang Y, Bhunia S, Mishra P. Scalable Test Generation for Trojan Detection Using Side Channel Analysis Ieee Transactions On Information Forensics and Security. 13: 2746-2760. DOI: 10.1109/Tifs.2018.2833059 |
0.327 |
|
2017 |
Karam R, Majerus SJA, Bourbeau DJ, Damaser MS, Bhunia S. Tunable and Lightweight On-Chip Event Detection for Implantable Bladder Pressure Monitoring Devices. Ieee Transactions On Biomedical Circuits and Systems. PMID 29028208 DOI: 10.1109/Tbcas.2017.2748981 |
0.335 |
|
2017 |
Chen C, Zhang F, Bhunia S, Mandal S. Broadband quantitative NQR for authentication of vitamins and dietary supplements. Journal of Magnetic Resonance (San Diego, Calif. : 1997). 278: 67-79. PMID 28371759 DOI: 10.1016/J.Jmr.2017.03.011 |
0.302 |
|
2017 |
Karam R, Paul S, Puri R, Bhunia S. Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications Acm Journal On Emerging Technologies in Computing Systems. 13: 1-24. DOI: 10.1145/2997649 |
0.353 |
|
2017 |
Basak A, Bhunia S, Tkacik T, Ray S. Security Assurance for System-on-Chip Designs With Untrusted IPs Ieee Transactions On Information Forensics and Security. 12: 1515-1528. DOI: 10.1109/Tifs.2017.2658544 |
0.372 |
|
2017 |
Bhunia S, Chen A, Sinanoglu O, M. Fung J. Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities Ieee Transactions On Emerging Topics in Computing. 5: 302-303. DOI: 10.1109/Tetc.2017.2738978 |
0.34 |
|
2017 |
Guin U, Bhunia S, Forte D, Tehranipoor MM. SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware Ieee Transactions On Dependable and Secure Computing. 14: 265-278. DOI: 10.1109/Tdsc.2016.2615609 |
0.307 |
|
2017 |
Qian W, Chen P, Karam R, Gao L, Bhunia S, Yu S. Energy-Efficient Adaptive Computing With Multifunctional Memory Ieee Transactions On Circuits and Systems Ii: Express Briefs. 64: 191-195. DOI: 10.1109/Tcsii.2016.2554958 |
0.337 |
|
2017 |
Shin D, Park J, Park J, Paul S, Bhunia S. Adaptive ECC for Tailored Protection of Nanoscale Memory Ieee Design & Test. 34: 84-93. DOI: 10.1109/Mdat.2016.2615844 |
0.518 |
|
2017 |
Stitt G, Karam R, Yang K, Bhunia S. A Uniquified Virtualization Approach to Hardware Security Ieee Embedded Systems Letters. 9: 53-56. DOI: 10.1109/Les.2017.2679183 |
0.316 |
|
2016 |
Xiao K, Forte D, Jin Y, Karri R, Bhunia S, Tehranipoor M. Hardware trojans: Lessons learned after one decade of research Acm Transactions On Design Automation of Electronic Systems. 22. DOI: 10.1145/2906147 |
0.336 |
|
2016 |
Qian W, Babecki C, Karam R, Paul S, Bhunia S. ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2578933 |
0.364 |
|
2016 |
Karam R, Puri R, Bhunia S. Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2555984 |
0.414 |
|
2016 |
Zheng Y, Zhang F, Bhunia S. DScanPUF: A delay-based physical unclonable function built into scan chain Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 24: 1059-1070. DOI: 10.1109/Tvlsi.2015.2421933 |
0.469 |
|
2016 |
Basak A, Bhunia S. P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1067-1078. DOI: 10.1109/Tcad.2015.2501311 |
0.371 |
|
2016 |
Zheng Y, Yang S, Bhunia S. SeMIA: Self-Similarity-Based IC Integrity Analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 37-48. DOI: 10.1109/Tcad.2015.2449231 |
0.402 |
|
2016 |
Babecki C, Qian W, Paul S, Karam R, Bhunia S. An embedded memory-centric reconfigurable hardware accelerator for security applications Ieee Transactions On Computers. 65: 3196-3202. DOI: 10.1109/Tc.2015.2512858 |
0.377 |
|
2016 |
Forte D, Perez R, Kim Y, Bhunia S. Supply-Chain Security for Cyberinfrastructure [Guest editors' introduction] Computer. 49: 12-16. DOI: 10.1109/Mc.2016.260 |
0.307 |
|
2016 |
Hoque T, Narasimhan S, Wang X, Mal-Sarkar S, Bhunia S. Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise Journal of Electronic Testing. 33: 107-124. DOI: 10.1007/S10836-016-5632-Y |
0.408 |
|
2015 |
Zhang F, Hennessy A, Bhunia S. Robust counterfeit PCB detection exploiting intrinsic trace impedance variations Proceedings of the Ieee Vlsi Test Symposium. 2015. DOI: 10.1109/VTS.2015.7116294 |
0.303 |
|
2015 |
Paul S, Krishna A, Qian W, Karam R, Bhunia S. MAHA: An energy-efficient malleable hardware accelerator for data-intensive applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1005-1016. DOI: 10.1109/Tvlsi.2014.2332538 |
0.38 |
|
2015 |
Zheng Y, Wang X, Bhunia S. SACCI: Scan-based characterization through clock phase sweep for counterfeit chip detection Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 831-841. DOI: 10.1109/Tvlsi.2014.2326556 |
0.453 |
|
2015 |
Yueh W, Chatterjee S, Zia M, Bhunia S, Mukhopadhyay S. A memory-based logic block with optimized-for-read SRAM for energy-efficient reconfigurable computing fabric Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 593-597. DOI: 10.1109/Tcsii.2015.2407792 |
0.566 |
|
2015 |
Wang X, Zheng Y, Basak A, Bhunia S. IIPS: Infrastructure IP for secure SoC design Ieee Transactions On Computers. 64: 2226-2238. DOI: 10.1109/Tc.2014.2360535 |
0.402 |
|
2015 |
Ghosh S, Basak A, Bhunia S. How secure are printed circuit boards Trojan attacks? Ieee Design and Test. 32: 7-16. DOI: 10.1109/Mdat.2014.2347918 |
0.633 |
|
2015 |
Roy K, Fan D, Fong X, Kim Y, Sharad M, Paul S, Chatterjee S, Bhunia S, Mukhopadhyay S. Exploring Spin Transfer Torque Devices for Unconventional Computing Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2015.2405171 |
0.716 |
|
2015 |
Mukhopadhyay S, Bhunia S, Hunter HC, Roy K. Guest editorial computing in emerging technologies (second issue) Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 5: 1-4. DOI: 10.1109/Jetcas.2015.2403551 |
0.611 |
|
2015 |
He T, Zhang F, Bhunia S, Feng PXL. Silicon Carbide (SiC) nanoelectromechanical antifuse for Ultralow-Power One-Time-Programmable (OTP) FPGA interconnects Ieee Journal of the Electron Devices Society. 3: 323-335. DOI: 10.1109/Jeds.2015.2421301 |
0.433 |
|
2015 |
Chen W, Lu W, Long B, Li Y, Gilmer D, Bersuker G, Bhunia S, Jha R. Switching characteristics of W/Zr/HfO2/TiN ReRAM devices for multi-level cell non-volatile memory applications Semiconductor Science and Technology. 30. DOI: 10.1088/0268-1242/30/7/075002 |
0.327 |
|
2014 |
Zheng Y, Basak A, Bhunia S. CACI: Dynamic current analysis towards robust recycled chip identification Proceedings - Design Automation Conference. DOI: 10.1145/2593069.2593102 |
0.343 |
|
2014 |
Mal-Sarkar S, Krishna A, Ghosh A, Bhunia S. Hardware trojan attacks in FPGA devices: Threat analysis and effective counter measures Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 287-292. DOI: 10.1145/2591513.2591520 |
0.314 |
|
2014 |
Paul S, Mukhopadhyay S, Bhunia S. A variation-aware preferential design approach for memory-based reconfigurable computing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2449-2461. DOI: 10.1109/Tvlsi.2013.2295538 |
0.593 |
|
2014 |
Ghosh A, Paul S, Park J, Bhunia S. Improving energy efficiency in FPGA through judicious mapping of computation to embedded memory blocks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1314-1327. DOI: 10.1109/Tvlsi.2013.2271696 |
0.527 |
|
2014 |
Park J, Bhunia S. VL-ECC: Variable data-length error correction code for embedded memory in DSP applications Ieee Transactions On Circuits and Systems Ii: Express Briefs. 61: 120-124. DOI: 10.1109/Tcsii.2013.2291091 |
0.538 |
|
2014 |
Mukhopadhyay S, Bhunia S, Hunter HC, Roy K. Guest editorial computing in emerging technologies (First issue) Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 4: 377-379. DOI: 10.1109/JETCAS.2014.2361417 |
0.335 |
|
2014 |
Paul S, Mukhopadhyay S, Bhunia S. Robust low-power reconfigurable computing with a variation-aware preferential design approach Icicdt 2014 - Ieee International Conference On Integrated Circuit Design and Technology. DOI: 10.1109/ICICDT.2014.6838621 |
0.335 |
|
2013 |
Zheng Y, Hashemian MS, Bhunia S. RESP: A robust physical unclonable function retrofitted into embedded SRAM array Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488807 |
0.363 |
|
2013 |
Narasimhan S, Du D, Chakraborty RS, Paul S, Wolff FG, Papachristou CA, Roy K, Bhunia S. Hardware trojan detection by multiple-parameter side-channel analysis Ieee Transactions On Computers. 62: 2183-2195. DOI: 10.1109/Tc.2012.200 |
0.565 |
|
2013 |
Bhunia S, Abramovici M, Agrawal D, Hsiao MS, Plusquellic J, Tehranipoor M, Bradley P. Protection against hardware trojan attacks: Towards a comprehensive solution Ieee Design and Test. 30: 6-17. DOI: 10.1109/Mdt.2012.2196252 |
0.355 |
|
2013 |
Bhunia S, Agrawal D, Nazhandali L. Guest editors' introduction: Trusted system-on-chip with untrusted components Ieee Design and Test. 30: 5-7. DOI: 10.1109/Mdat.2013.2258093 |
0.391 |
|
2013 |
Zheng Y, Krishna AR, Bhunia S. ScanPUF: Robust ultralow-overhead PUF using scan chain Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 626-631. DOI: 10.1109/ASPDAC.2013.6509668 |
0.336 |
|
2012 |
Lee J, Bhagavatula S, Bhunia S, Roy K, Jung B. Self-healing design in deep scaled CMOS technologies Journal of Circuits, Systems and Computers. 21. DOI: 10.1142/S0218126612400117 |
0.562 |
|
2012 |
Paul S, Bhunia S. A Scalable Memory-Based Reconfigurable Computing Framework for Nanoscale Crossbar Ieee Transactions On Nanotechnology. 11: 451-462. DOI: 10.1109/Tnano.2010.2041556 |
0.435 |
|
2012 |
Narasimhan S, Kunaparaju K, Bhunia S. Healing of DSP circuits under power bound using post-silicon operand bitwidth truncation Ieee Transactions On Circuits and Systems I: Regular Papers. 59: 1932-1941. DOI: 10.1109/Tcsi.2011.2180447 |
0.478 |
|
2012 |
Narasimhan S, Yueh W, Wang X, Mukhopadhyay S, Bhunia S. Improving IC security against trojan attacks through integration of security monitors Ieee Design and Test of Computers. 29: 37-46. DOI: 10.1109/Mdt.2012.2210183 |
0.603 |
|
2011 |
Narasimhan S, Chiel HJ, Bhunia S. Ultra-low-power and robust digital-signal-processing hardware for implantable neural interface microsystems. Ieee Transactions On Biomedical Circuits and Systems. 5: 169-78. PMID 23851205 DOI: 10.1109/Tbcas.2010.2076281 |
0.454 |
|
2011 |
Bhunia SS, Roy KK, Saxena AK. Profiling the structural determinants for the selectivity of representative factor-Xa and thrombin inhibitors using combined ligand-based and structure-based approaches. Journal of Chemical Information and Modeling. 51: 1966-85. PMID 21761917 DOI: 10.1021/Ci200185Q |
0.324 |
|
2011 |
Roy KK, Bhunia SS, Saxena AK. CoMFA, CoMSIA, and docking studies on thiolactone-class of potent anti-malarials: identification of essential structural features modulating anti-malarial activity. Chemical Biology & Drug Design. 78: 483-93. PMID 21672165 DOI: 10.1111/J.1747-0285.2011.01158.X |
0.333 |
|
2011 |
Paul S, Bhunia S. Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1368-1379. DOI: 10.1109/Tvlsi.2010.2049389 |
0.406 |
|
2011 |
Paul S, Mukhopadhyay S, Bhunia S. A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA Ieee Transactions On Nanotechnology. 10: 385-394. DOI: 10.1109/Tnano.2010.2041555 |
0.649 |
|
2011 |
Paul S, Cai F, Zhang X, Bhunia S. Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache Ieee Transactions On Computers. 60: 20-34. DOI: 10.1109/Tc.2010.203 |
0.39 |
|
2011 |
Paul S, Chatterjee S, Mukhopadhyay S, Bhunia S. Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 369-380. DOI: 10.1109/Jetcas.2011.2165232 |
0.617 |
|
2011 |
Chakraborty RS, Bhunia S. Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation Journal of Electronic Testing. 27: 767-785. DOI: 10.1007/S10836-011-5255-2 |
0.464 |
|
2010 |
Lee TH, Bhunia S, Mehregany M. Electromechanical computing at 500 degrees C with silicon carbide. Science (New York, N.Y.). 329: 1316-8. PMID 20829479 DOI: 10.1126/Science.1192511 |
0.355 |
|
2010 |
Bhunia S. A Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3–7 January 2010 Journal of Low Power Electronics. 6: 375-375. DOI: 10.1166/Jolpe.2010.1087 |
0.362 |
|
2010 |
Paul S, Mahmoodi H, Bhunia S. Low-overhead
F
max
calibration at multiple operating points using delay-sensitivity-based path selection Acm Transactions On Design Automation of Electronic Systems. 15: 1-34. DOI: 10.1145/1698759.1698769 |
0.429 |
|
2010 |
Ndai P, Rafique N, Thottethodi M, Ghosh S, Bhunia S, Roy K. Trifecta: A nonspeculative scheme to exploit common, data-dependent subcritical paths Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 53-65. DOI: 10.1109/Tvlsi.2008.2007491 |
0.768 |
|
2010 |
Bhunia S, Rao R. Guest Editors' Introduction: Managing Uncertainty through Postfabrication Calibration and Repair Ieee Design & Test of Computers. 27: 4-5. DOI: 10.1109/Mdt.2010.134 |
0.36 |
|
2009 |
Narasimhan S, Chiel HJ, Bhunia S. A preferential design approach for energy-efficient and robust implantable neural signal processing hardware. Conference Proceedings : ... Annual International Conference of the Ieee Engineering in Medicine and Biology Society. Ieee Engineering in Medicine and Biology Society. Annual Conference. 2009: 6383-6. PMID 19964418 DOI: 10.1109/IEMBS.2009.5333729 |
0.332 |
|
2009 |
Chakraborty RS, Bhunia S. A study of asynchronous design methodology for robust CMOS-nano hybrid system design Acm Journal On Emerging Technologies in Computing Systems. 5: 1-22. DOI: 10.1145/1568485.1568486 |
0.481 |
|
2009 |
Chakraborty R, Bhunia S. HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1493-1502. DOI: 10.1109/Tcad.2009.2028166 |
0.452 |
|
2009 |
Chakraborty R, Paul S, Zhou Y, Bhunia S. Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping Iet Computers & Digital Techniques. 3: 609. DOI: 10.1049/Iet-Cdt.2008.0135 |
0.445 |
|
2008 |
Datta A, Bhunia S, Choi JH, Mukhopadhyay S, Roy K. Profit Aware Circuit Design Under Process Variations Considering Speed Binning Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 806-815. DOI: 10.1109/Tvlsi.2008.2000364 |
0.739 |
|
2008 |
Ndai P, Bhunia S, Agarwal A, Roy K. Within-die variation-aware scheduling in superscalar processors for improved throughput Ieee Transactions On Computers. 57: 940-951. DOI: 10.1109/Tc.2008.40 |
0.776 |
|
2008 |
Bhunia S, Mahmoodi H, Raychowdhury A, Roy K. Arbitrary two-pattern delay testing using a low-overhead supply gating technique Journal of Electronic Testing: Theory and Applications (Jetta). 24: 577-590. DOI: 10.1007/S10836-008-5072-4 |
0.698 |
|
2007 |
Ghosh S, Bhunia S, Roy K. Low-Power and testable circuit synthesis using Shannon decomposition Acm Transactions On Design Automation of Electronic Systems. 12: 47. DOI: 10.1145/1278349.1278360 |
0.696 |
|
2007 |
Agarwal A, Kang K, Bhunia S, Gallagher JD, Roy K. Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 660-671. DOI: 10.1109/Tvlsi.2007.898683 |
0.641 |
|
2007 |
Chakraborty RS, Narasimhan S, Bhunia S. Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 2480-2488. DOI: 10.1109/Tcsi.2007.907828 |
0.464 |
|
2007 |
Ghosh S, Bhunia S, Roy K. CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1947-1956. DOI: 10.1109/Tcad.2007.896305 |
0.73 |
|
2007 |
Ghosh S, NDai P, Bhunia S, Roy K. Tolerance to small delay defects by adaptive clock stretching Proceedings - Iolts 2007 13th Ieee International On-Line Testing Symposium. 244-249. DOI: 10.1109/IOLTS.2007.67 |
0.808 |
|
2006 |
Banerjee N, Raychowdhury A, Roy K, Bhunia S, Mahmoodi H. Novel low-overhead operand isolation techniques for low-power datapath synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1034-1039. DOI: 10.1109/Tvlsi.2006.884054 |
0.743 |
|
2006 |
Ghosh S, Bhunia S, Raychowdhury A, Roy K. A novel delay fault testing methodology using low-overhead built-in delay sensor Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2934-2943. DOI: 10.1109/Tcad.2006.882523 |
0.742 |
|
2006 |
Datta A, Bhunia S, Mukhopadhyay S, Roy K. Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2427-2436. DOI: 10.1109/Tcad.2006.873886 |
0.738 |
|
2006 |
Mukhopadhyay S, Bhunia S, Roy K. Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1486-1495. DOI: 10.1109/Tcad.2005.855934 |
0.65 |
|
2006 |
Ghosh S, Bhunia S, Raychowdhury A, Roy K. Delay fault localization in test-per-scan BIST using built-in delay sensor Proceedings - Iolts 2006: 12th Ieee International On-Line Testing Symposium. 2006: 31-36. DOI: 10.1109/IOLTS.2006.19 |
0.642 |
|
2005 |
Chiou L, Bhunia S, Roy K. Synthesis of application-specific highly efficient multi-mode cores for embedded systems Acm Transactions On Embedded Computing Systems (Tecs). 4: 168-188. DOI: 10.1145/1053271.1053278 |
0.709 |
|
2005 |
Raychowdhury A, Paul BC, Bhunia S, Roy K. Computing with subthreshold leakage: Device/circuit/architecture co-design for ultralow-power subthreshold operation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1213-1223. DOI: 10.1109/Tvlsi.2005.859590 |
0.712 |
|
2005 |
Chen Q, Mahmoodi H, Bhunia S, Roy K. Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations Ieee Transactions On Very Large Scale Integration Systems. 13: 1286-1295. DOI: 10.1109/Tvlsi.2005.859565 |
0.65 |
|
2005 |
Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K. Low-power scan design using first-level supply gating Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 384-395. DOI: 10.1109/Tvlsi.2004.842885 |
0.68 |
|
2005 |
Bhunia S, Roy K. A novel wavelet transform-based transient current analysis for fault detection and localization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 503-507. DOI: 10.1109/Tvlsi.2004.842880 |
0.519 |
|
2005 |
Bhunia S, Datta A, Banerjee N, Roy K. GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks Ieee Transactions On Computers. 54: 752-766. DOI: 10.1109/Tc.2005.99 |
0.746 |
|
2005 |
Raychowdhury A, Ghosh S, Bhunia S, Ghosh D, Roy K. A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points Proceedings of the 10th Ieee European Test Symposium, Ets 2005. 2005: 108-113. DOI: 10.1109/ETS.2005.2 |
0.652 |
|
2005 |
Bhunia S, Mahmoodi H, Raychowdhury A, Roy K. A novel low-overhead delay testing technique for arbitrary two-pattern test application Proceedings -Design, Automation and Test in Europe, Date '05. 1136-1141. DOI: 10.1109/DATE.2005.27 |
0.7 |
|
2005 |
Bhunia S, Raychowdhury A, Roy K. Frequency specification testing of analog filters using wavelet transform of dynamic supply current Journal of Electronic Testing: Theory and Applications (Jetta). 21: 243-255. DOI: 10.1007/s10836-005-6354-8 |
0.609 |
|
2005 |
Bhunia S, Raychowdhury A, Roy K. Defect oriented testing of analog circuits using wavelet analysis of dynamic supply current Journal of Electronic Testing: Theory and Applications (Jetta). 21: 147-159. DOI: 10.1007/S10836-005-6144-3 |
0.672 |
|
2004 |
Li H, Bhunia S, Chen Y, Roy K, Vijaykumar TN. DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 245-254. DOI: 10.1109/TVLSI.2004.824307 |
0.527 |
|
2004 |
Bhunia S, Raychowdhury A, Roy K. Trim bit setting of analog filters using wavelet-based supply current analysis Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 708-709. DOI: 10.1109/DATE.2004.1268941 |
0.614 |
|
2003 |
Li H, Bhunia S, Chen Y, Vijaykumar TN, Roy K. Deterministic clock gating for microprocessor power reduction Proceedings - International Symposium On High-Performance Computer Architecture. 12: 113-122. DOI: 10.1109/HPCA.2003.1183529 |
0.537 |
|
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