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Vijaykrishnan Narayanan - Publications

Affiliations: 
Pennsylvania State University, State College, PA, United States 
Area:
Computer Science
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49 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Zhong H, Gu M, Wang Y, Liu Y, Narayanan V, Yang H, Li X. One-Shot Refresh: A Low-Power Low-Congestion Approach for Dynamic Memories Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1. DOI: 10.1109/Tcsii.2020.2988301  0.335
2020 Anderson S, Challapalle N, Sampson J, Narayanan V. Adaptive Neural Network Architectures for Power Aware Inference Ieee Design & Test of Computers. 37: 66-75. DOI: 10.1109/Mdat.2019.2947258  0.382
2019 Liang Y, Zhu Z, Li X, Gupta SK, Datta S, Narayanan V. Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 2855-2860. DOI: 10.1109/Tvlsi.2019.2932268  0.438
2019 Rangachar Srinivasa S, Ramanathan AK, Li X, Chen W, Gupta SK, Chang M, Ghosh S, Sampson J, Narayanan V. ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support Ieee Transactions On Circuits and Systems I: Regular Papers. 66: 2533-2545. DOI: 10.1109/Tcsi.2019.2897497  0.397
2019 Li X, Wu J, Ni K, George S, Ma K, Sampson J, Gupta SK, Liu Y, Yang H, Datta S, Narayanan V. Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs Ieee Design & Test of Computers. 36: 39-45. DOI: 10.1109/Mdat.2019.2902094  0.376
2019 Yoon I, Khan A, Datta S, Raychowdhury A, Chang M, Ni K, Jerry M, Gangopadhyay S, Smith GH, Hamam T, Romberg J, Narayanan V. A FerroFET-Based In-Memory Processor for Solving Distributed and Iterative Optimizations via Least-Squares Method Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: 132-141. DOI: 10.1109/Jxcdc.2019.2930222  0.323
2018 George S, Li X, Liao MJ, Ma K, Srinivasa S, Mohan K, Aziz A, Sampson J, Gupta SK, Narayanan V. Symmetric 2-D-Memory Access to Multidimensional Data Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 1040-1050. DOI: 10.1109/Tvlsi.2018.2801302  0.323
2018 Srinivasa S, Li X, Chang M, Sampson J, Gupta SK, Narayanan V. Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 671-683. DOI: 10.1109/Tvlsi.2017.2787562  0.357
2018 Liang Y, Li X, Gupta SK, Datta S, Narayanan V. Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model Ieee Transactions On Electron Devices. 65: 5525-5529. DOI: 10.1109/Ted.2018.2875661  0.306
2018 Liang Y, Li X, George S, Srinivasa S, Zhu Z, Gupta SK, Datta S, Narayanan V. Influence of Body Effect on Sample-and-Hold Circuit Design Using Negative Capacitance FET Ieee Transactions On Electron Devices. 65: 3909-3914. DOI: 10.1109/Ted.2018.2852679  0.375
2018 Li X, George S, Liang Y, Ma K, Ni K, Aziz A, Gupta SK, Sampson J, Chang M, Liu Y, Yang H, Datta S, Narayanan V. Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops Ieee Transactions On Electron Devices. 65: 2670-2674. DOI: 10.1109/Ted.2018.2829348  0.438
2018 Ma K, Li J, Li X, Liu Y, Xie Y, Kandemir M, Sampson J, Narayanan V. IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors Ieee Micro. 38: 11-19. DOI: 10.1109/Mm.2018.043191121  0.374
2017 Gala N, Krithivasan S, Tsai W, Li X, Narayanan V, Kamakoti V. An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators Acm Journal On Emerging Technologies in Computing Systems. 14: 1-28. DOI: 10.1145/3094263  0.399
2017 Ma K, Li X, Liu H, Sheng X, Wang Y, Swaminathan K, Liu Y, Xie Y, Sampson J, Narayanan V. Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems Acm Transactions in Embedded Computing Systems. 16: 107. DOI: 10.1145/3077575  0.592
2017 Li Y, Huang C, Wu C, Chen Y, Wang C, Datta S, Narayanan V. Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays Ieee Transactions On Very Large Scale Integration Systems. 25: 1477-1489. DOI: 10.1109/Tvlsi.2016.2639533  0.334
2017 Gupta S, Steiner M, Aziz A, Narayanan V, Datta S, Gupta SK. Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic Ieee Transactions On Electron Devices. 64: 3092-3100. DOI: 10.1109/Ted.2017.2717929  0.343
2017 Li X, Sampson J, Khan A, Ma K, George S, Aziz A, Gupta SK, Salahuddin S, Chang M, Datta S, Narayanan V. Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET Ieee Transactions On Electron Devices. 64: 3452-3458. DOI: 10.1109/Ted.2017.2716338  0.446
2017 Li X, Ma K, George S, Khwa W, Sampson J, Gupta S, Liu Y, Chang M, Datta S, Narayanan V. Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore Ieee Transactions On Electron Devices. 64: 3037-3040. DOI: 10.1109/Ted.2017.2707664  0.421
2017 Li X, George S, Ma K, Tsai W, Aziz A, Sampson J, Gupta SK, Chang M, Liu Y, Datta S, Narayanan V. Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops Ieee Transactions On Circuits and Systems I: Regular Papers. 64: 2907-2919. DOI: 10.1109/Tcsi.2017.2702741  0.437
2017 Tsai W, Barch DR, Cassidy AS, DeBole MV, Andreopoulos A, Jackson BL, Flickner MD, Arthur JV, Modha DS, Sampson J, Narayanan V. Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor Ieee Transactions On Computers. 66: 996-1007. DOI: 10.1109/Tc.2016.2630683  0.411
2016 Kim MS, Cane-Wissing W, Li X, Sampson J, Datta S, Gupta SK, Narayanan V. Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells Acm Journal On Emerging Technologies in Computing Systems. 12. DOI: 10.1145/2914790  0.388
2016 Ho CH, Chen YC, Wang CY, Huang CY, Datta S, Narayanan V. Area-aware decomposition for single-electron transistor arrays Acm Transactions On Design Automation of Electronic Systems. 21. DOI: 10.1145/2898998  0.332
2016 Xiao Y, Advani S, Shin D, Chang N, Sampson J, Narayanan V. A Saliency-Driven LCD Power Management System Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2520392  0.395
2016 Srinivasa S, Aziz A, Shukla N, Li X, Sampson J, Datta S, Kulkarni JP, Narayanan V, Gupta SK. Correlated Material Enhanced SRAMs With Robust Low Power Operation Ieee Transactions On Electron Devices. 63: 4744-4752. DOI: 10.1109/Ted.2016.2621125  0.387
2016 Ma K, Li X, Swaminathan K, Zheng Y, Li S, Liu Y, Xie Y, Sampson JJ, Narayanan V. Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power Ieee Micro. 36: 72-83. DOI: 10.1109/Mm.2016.35  0.606
2015 Kim MS, Li X, Liu H, Sampson J, Datta S, Narayanan V. Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2500160  0.46
2015 Liu CW, Chiang CE, Huang CY, Chen YC, Wang CY, Datta S, Narayanan V. Synthesis for Width Minimization in the Single-Electron Transistor Array Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2014.2386331  0.351
2015 Liu L, Li X, Narayanan V, Datta S. A Reconfigurable Low-Power BDD Logic Architecture Using Ferroelectric Single-Electron Transistors Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2395252  0.428
2015 Ma K, Li X, Li S, Liu Y, Sampson JJ, Xie Y, Narayanan V. Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications Ieee Micro. 35: 32-40. DOI: 10.1109/Mm.2015.88  0.427
2014 Kim MS, Liu H, Li X, Datta S, Narayanan V. A steep-slope tunnel FET based SAR analog-to-digital converter Ieee Transactions On Electron Devices. 61: 3661-3667. DOI: 10.1109/Ted.2014.2359663  0.421
2014 Pandey R, Rajamohanan B, Liu H, Narayanan V, Datta S. Electrical noise in heterojunction interband tunnel FETs Ieee Transactions On Electron Devices. 61: 552-560. DOI: 10.1109/Ted.2013.2293497  0.325
2014 Liu H, Cotter M, Datta S, Narayanan V. Soft-error performance evaluation on emerging low power devices Ieee Transactions On Device and Materials Reliability. 14: 732-741. DOI: 10.1109/Tdmr.2014.2316505  0.413
2014 Zhan J, Stoimenov N, Ouyang J, Thiele L, Narayanan V, Xie Y. Optimizing the NoC slack through voltage and frequency scaling in hard real-time embedded systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1632-1643. DOI: 10.1109/Tcad.2014.2347921  0.374
2014 Pandey R, Saripalli V, Kulkarni JP, Narayanan V, Datta S. Impact of single trap random telegraph noise on heterojunction TFET SRAM stability Ieee Electron Device Letters. 35: 393-395. DOI: 10.1109/Led.2014.2300193  0.679
2014 Liu H, Li X, Vaddi R, Ma K, Datta S, Narayanan V. Tunnel FET RF rectifier design for energy harvesting applications Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 4: 400-411. DOI: 10.1109/Jetcas.2014.2361068  0.45
2014 Datta S, Liu H, Narayanan V. Tunnel FET technology: A reliability perspective Microelectronics Reliability. 54: 861-874. DOI: 10.1016/J.Microrel.2014.02.002  0.469
2013 Chen Y, Eachempati S, Wang C, Datta S, Xie Y, Narayanan V. A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays Acm Journal On Emerging Technologies in Computing Systems. 9: 5. DOI: 10.1145/2422094.2422099  0.414
2013 Swaminathan K, Kultursay E, Saripalli V, Narayanan V, Kandemir MT, Datta S. Steep-slope devices: From dark to dim silicon Ieee Micro. 33: 50-59. DOI: 10.1109/Mm.2013.75  0.712
2013 Mukundrajan R, Cotter M, Bae S, Saripalli V, Irwin MJ, Datta S, Narayanan V. Design of energy-efficient circuits and systems using tunnel field effect transistors Iet Circuits, Devices and Systems. 7: 294-303. DOI: 10.1049/Iet-Cds.2012.0387  0.711
2012 Park S, Al Maashri A, Irick KM, Chandrashekhar A, Cotter M, Chandramoorthy N, Debole M, Narayanan V. System-on-chip for biologically inspired vision applications Ipsj Transactions On System Lsi Design Methodology. 5: 71-95. DOI: 10.2197/Ipsjtsldm.5.71  0.339
2012 Yang S, Gupta P, Wolf M, Serpanos D, Narayanan V, Xie Y. Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling Acm Transactions in Embedded Computing Systems. 11: 62. DOI: 10.1145/2345770.2345774  0.4
2012 Singh P, Narayanan V, Landis DL. Targeted random test generation for power-aware multicore designs Acm Transactions On Design Automation of Electronic Systems. 17. DOI: 10.1145/2209291.2209298  0.316
2011 Yu CL, Irick K, Chakrabarti C, Narayanan V. Multidimensional DFT IP generator for FPGA platforms Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 755-764. DOI: 10.1109/Tcsi.2010.2078750  0.336
2011 Macii E, Narayanan V, Roy K. Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue) Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 205-207. DOI: 10.1109/Jetcas.2011.2162865  0.439
2011 Çelik C, Unlu K, Narayanan V, Irwin MJ. Soft error modeling and analysis of the Neutron Intercepting Silicon Chip (NISC) Nuclear Instruments & Methods in Physics Research Section a-Accelerators Spectrometers Detectors and Associated Equipment. 652: 370-373. DOI: 10.1016/J.Nima.2010.08.117  0.337
2009 Ragheb T, Ricketts A, Mondal M, Kirolos S, Links GM, Narayanan V, Massoud Y. Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers Ieee Transactions On Circuits and Systems. 56: 374-383. DOI: 10.1109/Tcsi.2008.2001372  0.363
2009 Mangalagiri P, Narayanan V. Lifetime reliability aware design flow techniques for dual-vdd based platform FPGAs Proceedings of the 2009 Ieee Computer Society Annual Symposium On Vlsi, Isvlsi 2009. 61-66. DOI: 10.1109/ISVLSI.2009.42  0.713
2007 Ünlü K, Narayanan V, Çetiner SM, Degalahal V, Irwin MJ. Neutron-induced soft error rate measurements in semiconductor memories Nuclear Instruments & Methods in Physics Research Section a-Accelerators Spectrometers Detectors and Associated Equipment. 579: 252-255. DOI: 10.1016/J.Nima.2007.04.049  0.341
2005 Narayanan V, Ghosh S, Jone W-, Das SR. A built-in self-testing method for embedded multiport memory arrays Ieee Transactions On Instrumentation and Measurement. 54: 1721-1738. DOI: 10.1109/Tim.2005.855093  0.331
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