Jean-Luc Gaudiot - US grants

The purpose of this research project is to attack the issues of programming and performance evaluation of multiprocessor systems. This is done by a systematic selection of several representative problems in the numerical as well as the non-numerical domain and their implementation on a machine based on Inmos Transputers. Comparison with off-the-shelf multiprocessors (e.g. Sequent and Alliant) will be undertaken. The work will proceed with theoretical efforts in developing highly programmable user environments as well as experimental work in assessing the validity of the functional parallel programming approach.

This award is to purchase an IBM 540 server and assorted peripheral devices to support research in design automation for single chip VLSI microprocessors, principles of design for high performance VLSI microprocessors, USC Macro Data-Flow project, data-driven approach to programming multiprocessor systems, neurobiology and simulation of neural nets for invariant object recognition. The University of Southern California will be investigating and evaluating multiprocessor systems for use in the next generation of computer systems. The departments of Electrical Engineering- Systems and Computer Science will be purchasing a server and assorted peripheral devices to support research projects which rely upon extensive simulation of complex hardware and software systems.

9510656 Jonckheere Traditional robustness issues in uncertain feedback systems analysis and design can be approached by considering the space of uncertain parameters cut into two pieces by the crossover hypersurface separating that part of the uncertainty where specifications are met from that part where specifications are not met. A crucial observation is that this separating hypersurface can get very complicated and complexity bounds on its homology can be found. In addition to the possibility of computing the u function from this geometric situation, structural instability of the hypersurface has indeed appeared to be the only way to explain the embarrassing problem of lack of continuity of the real u-function relative the "certain" parameters. A prototype code for simplicial algorithm construction and display of the hypersurface - using the emerging computational geometry technology - is already on the verge of becoming operational. The first objective of this proposal is to further develop this code into a more powerful, user-friendly one using state-of- the-art computational geometry, anisotropic gridding, etc. The second objective of this proposal is to develop algebraic code (Grobner basis) for singularity of the Nyguist map that could reveal the potential for structural instability of the hypersurface or lack of continuity of performance relative to rounding errors. Special attention will be devoted to singularity over a stratified uncertainty space. ***

This project is experimenting with languages, compilers, and architectures for large-scale multiprocessors based on functional programming and single assignment data structures. The project includes work at USC on translators for functional languages, and work at the University of Delaware on architectures and simulations. The key insight motivating the work is that functional programming can increase performance of multithreaded systems. One increase of performance comes from the ability to move threads among processors. Another is the possibility that single assignment data structures can be cached with no need for coherence traffic, potentially increasing performance of parallel systems. Research will include development of a program execution model and memory model, design of a cache management protocol for single-assignment data structures, translation of benchmarks such as SPLASH 2 into a functional language, and simulation of the benchmarks running on the new execution model with cache protocol. The goal is to measure the extent to which the new models and cache protocols provide a performance advantage over execution models that permit multiple assignments. This project is experimenting with languages, compilers, and architectures for large-scale multiprocessors based on functional programming and single assignment data structures. The project includes work at USC on translators for functional languages, and work at the University of Delaware on architectures and simulations. The key insight motivating the work is that functional programming can increase performance of multithreaded systems. One increase of performance comes from the ability to move threads among processors. Another is the possibility that single assignment data structures can be cached with no need for coherence traffic, potentially increasing performance of parallel systems. Research will include development of a program execution model and memory model, design of a cache management protocol for single-assignment data structures, translation of benchmarks such as SPLASH 2 into a functional language, and simulation of the benchmarks running on the new execution model with cache protocol. The goal is to measure the extent to which the new models and cache protocols provide a performance advantage over execution models that permit multiple assignments.

9815742
Gaudiot

This three-year award for US-France cooperative research in high performance computing involves Jean-Luc Gaudiot of the University of Southern California, Guang Gao of the University of Delaware and Christine Eisenbeis at the French National Institute for Research in Informatics and Applied Mathematics (INRIA) at Rocquencourt. The objective of their research is simulation of multithreaded multiprocessors for high performance computing. The project adds an international dimension to an active NSF grant on functional programming of multithreaded systems. The US-France collaboration focuses on simulation. The investigators propose to specify, design and implement a trace simulator and to identify the sources of parallelism within a computer program.

The US investigators bring to this collaboration expertise in processor architecture design, multithreaded architecture design and application. This is complemented by French expertise in parallel compilation, code analysis and optimization. The research addresses the development of more efficient memory for large-scale parallel scientific computing.

Most modern single processor architectures focus on exploiting instruction-level parallelism. However, despite continued performance improvements, there is increasing doubt that aggressive ILP architecture techniques would continue bringing the desired improvements and that there will come about a diminishing return in the performance of single-chip architectures.

Multithreaded execution models promise to exploit thread-level parallelism (TLP) beyond a pure ILP approach. Multithreading can be applied directly at the level of uniprocessor instruction-set architectures. For example, Simultaneous MultiThreading (SMT) is a promising approach, which is attracting the attention of a number of academic and industrial research groups. This technique allows the various pipelines of a "superscalar" processor to be efficiently utilized by scheduling from several "coarse-grain" threads of one (or several) program(s). Although exploiting both ILP and TLP is attractive, the following questions are investigated in the project:

- Can an architecture model, which integrates fine-grain multithreading support with a coarse-grain multithreaded architecture model such as SMT, be developed?

- What are the design trade-off when mapping these architecture features to single-chip implementations?

- What compiling methodology for the proposed architecture model would exploit thread-level parallelism at both coarse and fine-grain levels?

A new, completely-integrated processor-memory-interconnect (CI-PMI)
architecture model suitable for a range of data-intensive
applications is proposed. Compared to the existing processor-in-memory
(PIM) architectures, the proposed CI-PMI approach integrates more
completely the processing, memory, and interconnect. This is achieved
by starting with the classical architecture of high capacity memory,
namely, a binary tree of decoders with memory modules as leaves, laid
out as an H-tree. In the proposed model, copies of one or more types
of application-specific computing elements are added at different
levels of the memory decoder tree, desired functionality added to the
memory decoders to augment their role as interconnects as well as to
support desired computation, and, if necessary, additional interconnects
added between the application-specific processors, the memory modules,
and the decoders. The proposed architecture will be developed and
demonstrated for a data-intensive application, namely motion estimation
for MPEG encoding.

The results of the proposed research will be used to augment one
advanced class, to be taught at USC as well as UCI. The class will
take a top-down view of advanced processor-in-memory architectures
including those developed in this project.

The proposed research will advance the state of the art in computer
architecture, VLSI, and VLSI CAD, leading to faster and cheaper designs
for day to day computation and information retrieval, exchange, and
management.

This project, developing a Highly Interactive Parallelized Display Wall (HIPerWall) new visualization facility, aims at advancing the state of Earth Science modeling and visualization. HIPerWall is a high performance visualization system with a wall-sized ultra high-density tiled display that operates at the perception threshold of the human eye, allowing researchers to view and manipulate their data sets at resolutions commensurate with large-scale grids or dense sensor network data. The facility will be able to display extremely high-resolution datasets that will drive and provide focus for on-going research into management, transfer, and visualization of terabyte-scale data. By rapid, visual comparison of theory with experimental data, scientists should be able to swiftly validate and comprehend theory and practice. Although the proposed research is focused on Earth System Sciences, other research areas will benefit, including,
Computational Fluid Dynamics
Direct numerical simulation of turbulent chemically reacting and dispersed 2-phase flows,
Engineering Mechanics
System identification using 3D video tracking;
o Microwave imaging for damage visualization;
o Remote system monitoring,
Structural and Earthquake Engineering
o Advanced scientific visualization of dynamics of systems;
o Model-based simulation of experimental data from large and medium scale earthquake testing;
o Analysis of large-scale earthquake field data,
Materials and Devices
o Molecular modeling and visualization;
o Synthesis of structural materials and composites;
o Mathematical modeling of advanced materials and processes;
o Material characterization,
Embodied Interaction in Immersive Systems
o Novel sensor technologies and modes of interaction for cultural and technical applications,
Scientific Computing,
o Large scale data visualization;
o Storage, compression and access of stored real time simulation data;
o Image based rendering;
o 3D data reconstruction, and
Biomedical Engineering
o Computer simulation and tissue engineering;
o Imaging and image understanding.

Broader Impact: The facility, to be set in a large classroom, directly contributes to education through courses and recruiting efforts. The display wall benefits collaborations that have impact on areas such as homeland security and emergency response.

A Programmable, Efficient, and Dynamic Architecture and Compilation Framework for Networking Applications
Abstract

The research addresses two closely related concurrent execution models based on coarse-grained and fine-grained multithreading in the context of networking applications. The research will result in multithreaded architecture and execution models to handle the needs for programmability, scalability, dynamic workload handling, and storage intensive features of applications in this domain. In addition, appropriate compilation methods and tools under the proposed architecture execution models will be developed.

With increasing availability of multithreaded and multicore chip architectures the need for fundamental understanding of application decomposition, performance and programmability is a significant problem. The project will identify architectures, execution models, and software tools that address these issues based on a demanding set of networking applications.

The advent of new microprocessor chip architectures (e.g., GPUs, multi-core/many-core chips architectures), next generation large scale integrated problems such as datacenter applications points to the need for a comprehensive rethinking of the approach to architecture design, programming, and software design. The research proposed in this document will be concerned with the characteristic behavior of future applications, highlighted by the performance, scalability, and how computer systems (execution and architecture models, and compilers/runtime software technologies) can be appropriately targeted. This work will result in the characterization of the features and requirements of such applications, in the development of suitable execution and architecture models that match their needs, and in the development of a compilation technology and its associated tools that will work in coordination with the proposed architecture models for the targeted application domains. The outcome of the proposed research will be an in-depth understanding of the needs of future applications, the demonstration of new architecture ideas, as well as the design of compilation methods and tools.

Computer systems have undergone a fundamental transformation recently, from single‐core processors to devices with increasingly higher core counts within a single chip. The semi‐conductor industry now faces the infamous power and utilization walls, that is, physical constraints such as levels of power and energy consumption, but also reliability of the various components, must be taken into account not only during the chip fabrication process, but also when generating machine code and during program execution. To meet these challenges, heterogeneity in design, both at the architecture and technology levels, will be the prevailing approach for energy efficient computing as specialized cores, accelerators, and graphical processing units (GPUs) can eliminate the energy overheads of general‐purpose homogeneous cores. However, with future technological challenges pointing in the direction of on‐chip heterogeneity, and because of the traditional difficulty of parallel programming, it becomes imperative to produce new system software stacks that can take advantage of the heterogeneous hardware.

This project proposes to rethink the whole hardware‐software interface, by researching novel ways to design many‐core chip architectures and weaving heterogeneous components together and binding them by a fast and energy efficient on‐chip interconnection network. On top of it will lay a system software layer to efficiently drive applications and map them onto the best suited components of the chip. Both the hardware and software layer are encompassed by a novel execution model, which describes how to orchestrate the various parts of a program in the most efficient way (be it with respect to power and energy, performance, or reliability). To achieve these goals, the development of a new model of computation called SPARTA (Stream-based Processor And RunTime Architecture) is proposed. The proposed model combines a new runtime and compiler technology with a hierarchical heterogeneous many‐core chip and features hardware mechanisms for stream‐based fine‐grain program execution models to be reflected in different new software/hardware systems. Many issues are be envisioned, including programmability, scalability, performance evaluation, and power efficiency. Specifically, the goal is to identify the major challenges and obstacles toward an efficient exploitation of parallelism and scalability. To do so, traditional approaches will be re-evaluated by studying a collection of representative programs. A vertical design methodology is then proposed to effectively address the above challenges through the SPARTA approach and its implementation. In particular, the proposed cross-layer methodology consists of (a) a programming/execution model that will combine the Codelet model (leveraging our past research in dataflow models and extensions) with generalized streams: the Streaming Codelets, (b) an architecture model that will efficiently support the Streaming Codelets in heterogeneous hardware, and (c) a system software Stack that will be capable of effectively mapping Streaming Codelets to the proposed architecture. Finally, a qualitative and quantitative study of SPARTA will be performed via selected benchmarks and a consolidated methodology based on experimentation and analysis. The holistic cross-layer design methodology spanning the hardware/software stack and the reliability techniques developed from this research will significantly impact next generation multi‐core and System‐on‐Chip (SoC) architectures with improvements in energy efficiency, programmability, performance and robustness.

Traditional software-based antivirus cannot keep up with the rapidly increasing number of cyber-attacks. This project explores approaches to improve the security of computer systems using flexible hardware techniques. It focuses on defending cyber-attacks by building a flexible hardware-based malware detection system and developing a level of immunity for computer systems against viruses through novel hardware design.

This project aims to explore a viable path forward for developing future intrusion detection systems and designing secure computer systems. The detection system leverages malware features from both software and hardware and by applying advanced machine learning techniques to enhance the detection accuracy. The system is implemented with programmable hardware to achieve robust and adaptable hardware security enabling mechanism with low performance overhead for the ever-changing malware landscape. In addition, the project seeks ways to make the hardware itself more secure by providing software and architecture support for stronger isolation between applications from different security domains.

This project brings together research in the domains of security, computer architecture and machine learning to create a secure and trustworthy cyberspace. Additional broader impact includes the development of partnerships between our team and industry, and others (e.g., national laboratories). Potential research result transfer should help improve national security and result in increased economic competitiveness for the United States. It will also play a major role in education by integrating exploration with teaching and training, as well as making the necessary efforts to attract and train minority students.

The project repository will be indefinitely maintained at https://github.com/uci-pascal-satc/hardware-security/. All data will also be stored in the laboratory where the simulation and experiments are conducted. This will be done with standard backups using computers, external disks, and various storage media.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.