Sunil P. Khatri
Affiliations: | 2000-2004 | Electrical Engineering | University of Colorado, Boulder, Boulder, CO, United States |
2004- | Electrical and Computer Engineering | Texas A & M University, College Station, TX, United States |
Area:
Electronics and Electrical EngineeringWebsite:
https://people.engr.tamu.edu/sunilkhatri/index.htmlGoogle:
"Sunil P. Khatri"Bio:
https://www.proquest.com/openview/d605e825243283b91e1ffdf7ef70df3d/1
Parents
Sign in to add mentorRobert K. Brayton | grad student | 1999 | UC Berkeley | |
(Cross -talk noise immune VLSI design using regular layout fabrics) | ||||
Alberto L. Sangiovanni-Vincentelli | grad student | 1999 | UC Berkeley |
Children
Sign in to add traineeBrock J. LaMeres | grad student | 2005 | CU Boulder |
Sabyasachi Das | grad student | 2007 | CU Boulder |
Chunjie Duan | grad student | 2008 | CU Boulder |
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Publications
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Douglass AJ, Khatri SP. (2019) Fast, Ring-Based Design of 3-D Stacked DRAM Ieee Transactions On Very Large Scale Integration Systems. 27: 1731-1741 |
Al Kawam A, Datta A, Khatri S. (2018) A GPU-CPU heterogeneous algorithm for NGS read alignment International Journal of Computational Biology and Drug Design. 11: 52 |
Fairouz A, Abusultan M, Elshennawy A, et al. (2018) Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router Journal of Low Power Electronics. 14: 414-427 |
Fedorov VV, Abusultan M, Khatri SP. (2016) FTCAM: An Area-Efficient Flash-Based Ternary CAM Design Ieee Transactions On Computers. 65: 2652-2658 |
Fedorov VV, Abusultan M, Khatri SP. (2014) An area-efficient Ternary CAM design using floating gate transistors 2014 32nd Ieee International Conference On Computer Design, Iccd 2014. 55-60 |
Croix JF, Khatri SP, Gulati K. (2013) Using gpus to acceleratecad algorithms Ieee Design and Test. 30: 8-16 |
Turker DZ, Khatri SP, Sánchez-Sinencio E. (2011) A DCVSL delay cell for fast low power frequency synthesis applications Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1225-1238 |
Jayakumar N, Khatri SP. (2010) A simultaneous input vector control and circuit modification technique to reduce leakage with zero delay penalty Acm Transactions On Design Automation of Electronic Systems. 16 |
Gingl Z, Kish LB, Khatri SP. (2010) Towards brain-inspired computing Fluctuation and Noise Letters. 9: 403-412 |
Singh A, Gulati K, Khatri SP. (2010) Minimum leakage vector computation using weighted partial MaxSAT Midwest Symposium On Circuits and Systems. 201-204 |