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Xinnan Lin, Ph.D. - Publications

Affiliations: 
2007 Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong 
Area:
Electronics and Electrical Engineering
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32 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2021 Ding F, Dong D, Chen Y, Lin X, Zhang L. Robust Simulations of Nanoscale Phase Change Memory: Dynamics and Retention. Nanomaterials (Basel, Switzerland). 11. PMID 34835708 DOI: 10.3390/nano11112945  0.461
2020 He H, Xiong C, Yin J, Wang X, Lin X, Zhang S. Analytical Drain Current and Capacitance Model for Amorphous InGaZnO TFTs Considering Temperature Characteristics Ieee Transactions On Electron Devices. 67: 3637-3644. DOI: 10.1109/Ted.2020.3009086  0.378
2020 Hu H, Liu D, Chen X, Dong D, Cui X, Liu M, Lin X, Zhang L, Chan M. A Compact Phase Change Memory Model With Dynamic State Variables Ieee Transactions On Electron Devices. 67: 133-139. DOI: 10.1109/Ted.2019.2956193  0.622
2020 Chen X, Hu H, Huang X, Cai W, Liu M, Lam C, Lin X, Zhang L, Chan M. A SPICE Model of Phase Change Memory for Neuromorphic Circuits Ieee Access. 8: 95278-95287. DOI: 10.1109/Access.2020.2995907  0.633
2020 Li W, Lou H, Lin X. Investigation of trench process variation on the recessed-gate junctionless MOSFETs considering the circuit application Semiconductor Science and Technology. 35: 85002. DOI: 10.1088/1361-6641/Ab87Df  0.323
2019 Zhang L, Ma C, Xiao Y, Zhang H, Lin X, Chan M. A Dynamic Time Evolution Method for Concurrent Device-Circuit Aging Simulations Ieee Transactions On Electron Devices. 66: 184-190. DOI: 10.1109/Ted.2018.2882832  0.614
2018 Yang Y, Lou H, Lin X. High-k Spacer Consideration of Ultrascaled Gate-All-Around Junctionless Transistor in Ballistic Regime Ieee Transactions On Electron Devices. 65: 5282-5288. DOI: 10.1109/Ted.2018.2873717  0.395
2018 Wan W, Lou H, Xiao Y, Lin X. Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect Ieee Transactions On Electron Devices. 65: 1873-1879. DOI: 10.1109/Ted.2018.2812241  0.347
2018 Yuan M, Zhou H, Tseng Y, Chen P, Shih C, Huang H, Chang T, Cui X, Lin X, Zhang S. Enhancing the Electrical Uniformity and Reliability of the HfO2-Based RRAM Using High-Permittivity Ta2O5 Side Wall Ieee Journal of the Electron Devices Society. 6: 627-632. DOI: 10.1109/Jeds.2018.2833504  0.346
2018 Zhang L, Song D, Xiao Y, Lin X, Chan M. On the Formulation of Self-Heating Models for Circuit Simulation Ieee Journal of the Electron Devices Society. 6: 291-297. DOI: 10.1109/Jeds.2018.2801301  0.589
2017 Xu P, Lou H, Zhang L, Yu Z, Lin X. Compact Model for Double-Gate Tunnel FETs With Gate–Drain Underlap Ieee Transactions On Electron Devices. 64: 5242-5248. DOI: 10.1109/Ted.2017.2762861  0.596
2017 Wang P, Chen Y, Li S, Raju S, Wang L, Zhang L, Lin X, Song Z, Chan M. Low Power Phase Change Memory With Vertical Carbon Nanotube Electrode Ieee Journal of the Electron Devices Society. 5: 362-366. DOI: 10.1109/Jeds.2017.2734858  0.587
2017 Sun H, Liu M, Liu P, Lin X, Cui X, Chen J, Chen D. Performance optimization of lateral AlGaN/GaN HEMTs with cap gate on 150-mm silicon substrate Solid-State Electronics. 130: 28-32. DOI: 10.1016/J.Sse.2017.01.006  0.36
2017 Qi Y, Yu H, Zhang J, Zhang L, He C, Lin X. A compact dual-wavelength Nd:LuVO4 laser with adjustable power-ratio between 1064 nm and 1342 nm lines by controlling polarization dependent loss Optics Communications. 382: 302-306. DOI: 10.1016/J.Optcom.2016.07.035  0.34
2016 Chen D, Lin XX, Huang WH, Zhang W, Tan ZR, Peng JB, Wang YC, Guo Y, Hu DL, Chen Y. Sodium tanshinone IIA sulfonate and its interactions with human CYP450s. Xenobiotica; the Fate of Foreign Compounds in Biological Systems. 1-8. PMID 26932161 DOI: 10.3109/00498254.2016.1152417  0.415
2016 Ma C, Zhang L, Lin X, Chan M. Universal framework for temperature dependence prediction of the negative bias temperature instability based on microscope pictures Japanese Journal of Applied Physics. 55. DOI: 10.7567/Jjap.55.044201  0.484
2016 He H, Liu Y, Yan B, Lin X, Zheng X, Zhang S. Analytical Drain Current Model for Amorphous InGaZnO Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States Ieee Transactions On Electron Devices. 64: 3654-3660. DOI: 10.1109/Ted.2017.2721436  0.349
2016 Xiao Y, Lin X, Lou H, Zhang B, Zhang L, Chan M. A Short Channel Double-Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect Ieee Transactions On Electron Devices. 63: 4661-4667. DOI: 10.1109/Ted.2016.2620240  0.608
2016 Dong Y, Zhang L, Li X, Lin X, Chan M. A Compact Model for Double-Gate Heterojunction Tunnel FETs Ieee Transactions On Electron Devices. 63: 4506-4513. DOI: 10.1109/Ted.2016.2604001  0.649
2015 Li D, Zhang B, Lou H, Zhang L, Lin X, Chan M. Comparative Analysis of Carrier Statistics on MOSFET and Tunneling FET Characteristics Ieee Journal of the Electron Devices Society. 3: 447-451. DOI: 10.1109/Jeds.2015.2475163  0.637
2015 Chen J, Meng H, Jiang FXC, Lin X. A snapback-free shorted-anode insulated gate bipolar transistor with an N-path structure Superlattices and Microstructures. 78: 201-209. DOI: 10.1016/J.Spmi.2014.11.034  0.321
2014 Chen Y, Kwong KC, Lin X, Song Z, Chan M. 3-D resistance model for phase-change memory cell Ieee Transactions On Electron Devices. 61: 4098-4104. DOI: 10.1109/Ted.2014.2365012  0.688
2013 Lou H, Li D, Dong Y, Lin X, Yang S, He J, Chan M. Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors Japanese Journal of Applied Physics. 52: 104302. DOI: 10.7567/Jjap.52.104302  0.519
2013 Lou H, Li D, Dong Y, Lin X, He J, Yang S, Chan M. Suppression of tunneling leakage current in junctionless nanowire transistors Semiconductor Science and Technology. 28: 125016. DOI: 10.1088/0268-1242/28/12/125016  0.556
2012 Zhang L, Lin X, He J, Chan M. An Analytical Charge Model for Double-Gate Tunnel FETs Ieee Transactions On Electron Devices. 59: 3217-3223. DOI: 10.1109/Ted.2012.2217145  0.637
2012 Lou H, Zhang L, Zhu Y, Lin X, Yang S, He J, Chan M. A Junctionless Nanowire Transistor With a Dual-Material Gate Ieee Transactions On Electron Devices. 59: 1829-1836. DOI: 10.1109/Ted.2012.2192499  0.625
2012 Li L, Zhang L, Lin X, He J, Chui CO, Chan M. Phase-change memory with multifin thin-film-transistor driver technology Ieee Electron Device Letters. 33: 405-407. DOI: 10.1109/Led.2011.2181480  0.606
2011 Wang H, Ma C, Zhang C, Hel J, Liu Z, Lin X. Impact of random dopant fluctuation effect on surrounding gate MOSFETs: from atomic level simulation to circuit performance evaluation. Journal of Nanoscience and Nanotechnology. 11: 10429-32. PMID 22408920 DOI: 10.1166/Jnn.2011.3985  0.39
2010 Zhang L, Zhang J, Song Y, Lin X, He J, Chan M. Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect Microelectronics Reliability. 50: 1062-1070. DOI: 10.1016/J.Microrel.2010.04.005  0.641
2008 Ma C, Li B, Wei Y, Zhang L, He J, Zhang X, Lin X, Chan M. FinFET reliability study by forward gated-diode generation–recombination current Semiconductor Science and Technology. 23: 75008. DOI: 10.1088/0268-1242/23/7/075008  0.606
2004 Zhang S, Han R, Lin X, Wu X, Chan M. A stacked CMOS technology on SOI substrate Ieee Electron Device Letters. 25: 661-663. DOI: 10.1109/Led.2004.834735  0.531
2003 Zhang S, Lin X, Huang R, Han R, Chan M. A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application Ieee Transactions On Electron Devices. 50: 2297-2300. DOI: 10.1109/Ted.2003.818598  0.551
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