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Malou F, Gasiot G, Chevallier R, et al. (2014) TID and SEE characterization of Rad-Hardened 1.2GHz PLL IP from new ST CMOS 65nm space technology Ieee Radiation Effects Data Workshop. 2015
Malou F, Gasiot G, Chevallier R, et al. (2014) TID and SEE characterization of Rad-Hardened 1.2GHz PLL IP from new ST CMOS 65nm space technology Ieee Radiation Effects Data Workshop. 2015
Autran JL, Munteanu D, Sauze S, et al. (2014) Altitude and underground real-time ser testing of SRAMs manufactured in CMOS bulk 130, 65 and 40 nm Ieee Radiation Effects Data Workshop. 2015
Glorieux M, Clerc S, Gasiot G, et al. (2014) 65 nm fault tolerant latch architecture based on transient propagation blocking Ieee International Reliability Physics Symposium Proceedings. SE.1.1-SE.1.5
Glorieux M, Clerc S, Gasiot G, et al. (2014) 65 nm fault tolerant latch architecture based on transient propagation blocking Ieee International Reliability Physics Symposium Proceedings. SE.1.1-SE.1.5
Bottoni C, Glorieux M, Daveau JM, et al. (2014) Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor Ieee International Reliability Physics Symposium Proceedings. 5F.5.1-5F.5.6
Bottoni C, Glorieux M, Daveau JM, et al. (2014) Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor Ieee International Reliability Physics Symposium Proceedings. 5F.5.1-5F.5.6
Abouzeid F, Bienfait A, Akyel KC, et al. (2013) Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI European Solid-State Circuits Conference. 205-208
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