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Davide Pandini, Ph.D. - Publications

Affiliations: 
2001 Carnegie Mellon University, Pittsburgh, PA 
Area:
Electronics and Electrical Engineering
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31 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2013 Manuzzato A, Campi F, Liberali V, Pandini D. Design methodology for low-power embedded microprocessors 2013 23rd International Workshop On Power and Timing Modeling, Optimization and Simulation, Patmos 2013. 259-264. DOI: 10.1109/PATMOS.2013.6662187  0.351
2013 Manuzzato A, Campi F, Rossi D, Liberali V, Pandini D. Exploiting body biasing for leakage reduction: A case study Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 133-138. DOI: 10.1109/ISVLSI.2013.6654635  0.415
2012 Doriol PJ, Sanna A, Chandra A, Forzan C, Pandini D. SSO noise and conducted EMI: Modeling, analysis, and design solutions 2012 Ieee 16th Workshop On Signal and Power Integrity, Spi 2012 - Proceedings. 107-110. DOI: 10.1109/SaPIW.2012.6222922  0.39
2012 Forzan C, Valente P, Kumar A, Pandini D. Understanding and modeling the impact of analog IPs on System-on-Chip's EMI Ieee International Symposium On Electromagnetic Compatibility. DOI: 10.1109/EMCEurope.2012.6396875  0.42
2010 Andrikos N, Lavagno L, Campi F, Pandini D. Improving electro-magnetic interference of embedded systems through jittered-delay desynchronization Journal of Low Power Electronics. 6: 607-615. DOI: 10.1166/Jolpe.2010.1110  0.462
2010 Pilato C, Ferrandi F, Pandini D. A fast heuristic for extending standard cell libraries with regular macro cells Proceedings - Ieee Annual Symposium On Vlsi, Isvlsi 2010. 23-28. DOI: 10.1109/ISVLSI.2010.69  0.486
2009 Pandini D, Repetto GA, Sinisi V. Clock-tree synthesis for low-EMI design Journal of Embedded Computing. 3: 197-207. DOI: 10.3233/Jec-2009-0092  0.479
2009 Forzan C, Pandini D. Statistical static timing analysis: A survey Integration, the Vlsi Journal. 42: 409-435. DOI: 10.1016/J.Vlsi.2008.10.002  0.436
2009 Graziosi G, Doriol PJ, Villavicencio Y, Forzan C, Rotigni M, Pandini D. Advanced modeling techniques for system-level power integrity and EMC analysis 2009 European Microelectronics and Packaging Conference, Empc 2009.  0.383
2009 Doriol PJ, Villavicencio Y, Forzan C, Rotigni M, Graziosi G, Pandini D. EMC-aware design on a microcontroller for automotive applications Proceedings -Design, Automation and Test in Europe, Date. 1208-1213.  0.346
2007 Pandini D, Desoli G, Cremonesi A. Computing and design for software and silicon manufacturing 2007 Ifip International Conference On Very Large Scale Integration, Vlsi-Soc. 122-127. DOI: 10.1109/VLSISOC.2007.4402484  0.38
2007 Rosiello APE, Ferrandi F, Pandini D, Sciuto D. A hash-based approach for functional regularity extraction during logic synthesis Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 92-97. DOI: 10.1109/ISVLSI.2007.5  0.426
2007 Pandini D. Innovative design platforms for reliable SoCs in advanced nanometer technologies Proceedings - Iolts 2007 13th Ieee International On-Line Testing Symposium. 254. DOI: 10.1109/IOLTS.2007.41  0.516
2007 Forzan C, Pandini D. Why we need statistical static timing analysis 2007 Ieee International Conference On Computer Design, Iccd 2007. 91-96. DOI: 10.1109/ICCD.2007.4601885  0.401
2007 Andrikos N, Lavagno L, Pandini D, Sotiriou CP. A fully-automated desynchronization flow for synchronous circuits Proceedings - Design Automation Conference. 982-985. DOI: 10.1109/DAC.2007.375308  0.452
2007 Pandini D. Statistical static timing analysis: A new approach to deal with increased process variability in advanced nanometer technologies Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4644: 577.  0.329
2007 Pandini D, Repetto GA, Sinisi V. Clock distribution techniques for low-EMI design Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4644: 201-210.  0.415
2006 Pandini D, Repetto GA. Spectral analysis of the on-chip waveforms to generate guidelines for EMC-aware design Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4148: 532-542.  0.369
2006 Pandini D, Repetto GA. Clock-tree synthesis for EMC-aware design Proceedings of the Fourth Iasted International Conference On Circuits, Signals, and Systems, Css 2006. 137-143.  0.369
2005 Graziano M, Forzan C, Pandini D. Power supply selective mapping for accurate timing analysis Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3728: 267-276. DOI: 10.1166/Jolpe.2006.012  0.448
2005 Chakraborty A, Pandini D, Macii A, Macii E, Poncino M. Evaluating regularity extraction in logic synthesis Isscs 2005: International Symposium On Signals, Circuits and Systems - Proceedings. 2: 641-644. DOI: 10.1109/ISSCS.2005.1511322  0.45
2005 Graziano M, Forzan C, Pandini D. Including power supply variations into static timing analysis: Methodology and flow Proceedings - Ieee International Soc Conference. 229-232.  0.385
2004 Macchiarulo L, Caccamo CF, Pandini D. A comparison between mask- and field-programmable routing structures on industrial FPGA architectures Proceedings of the Acm Great Lakes Symposium On Vlsi. 436-439.  0.405
2004 Pandini D, Forzan C, Baldi L. Design methodologies and architecture solutions for high-performance interconnects Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 152-159.  0.478
2003 Pandini D, Pileggi LT, Strojwas AJ. Global and local congestion optimization in technology mapping Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 498-506. DOI: 10.1109/Tcad.2003.809646  0.63
2003 Pandini D, Pileggi LT, Strojwas AJ. Bounding the efforts on congestion optimization for physical synthesis Proceedings of the Ieee Great Lakes Symposium On Vlsi. 7-10.  0.633
2002 Pandini D, Pileggi LT, Strojwas AJ. Congestion-aware logic synthesis Proceedings -Design, Automation and Test in Europe, Date. 664-671. DOI: 10.1109/DATE.2002.998370  0.618
2002 Pandini D, Pileggi LT, Strojwas AJ. Understanding and addressing the impact of wiring congestion during technology mapping Proceedings of the International Symposium On Physical Design. 131-136.  0.646
2001 Baldi L, Franzini B, Pandini D, Zafalon R. Design solutions for the interconnection parasitic effects in deep sub-micron technologies Microelectronic Engineering. 55: 11-18. DOI: 10.1016/S0167-9317(00)00423-8  0.415
2000 Franzini B, Forzan C, Pandini D, Scandolara P, Dal Fabbro A. Crosstalk aware static timing analysis: A two step approach Proceedings - International Symposium On Quality Electronic Design, Isqed. 2000: 499-503. DOI: 10.1109/ISQED.2000.838935  0.404
1995 Malavasi E, Pandini D. Optimum CMOS Stack Generation with Analog Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 107-122. DOI: 10.1109/43.363120  0.301
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