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Joseph A. Zambreno, Ph.D. - Publications

Affiliations: 
2006 Northwestern University, Evanston, IL 
Area:
Computer Science, Electronics and Electrical Engineering
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31 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Olufowobi H, Young C, Zambreno J, Bloom G. SAIDuCANT: Specification-Based Automotive Intrusion Detection Using Controller Area Network (CAN) Timing Ieee Transactions On Vehicular Technology. 69: 1484-1494. DOI: 10.1109/Tvt.2019.2961344  0.392
2020 Saha S, Duwe H, Zambreno J. CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks Journal of Signal Processing Systems. 92: 907-929. DOI: 10.1007/S11265-020-01546-X  0.433
2019 Young C, Zambreno J, Olufowobi H, Bloom G. Survey of Automotive Controller Area Network Intrusion Detection Systems Ieee Design & Test of Computers. 36: 48-55. DOI: 10.1109/Mdat.2019.2899062  0.366
2018 Grieve A, Davies M, Jones PH, Zambreno J. ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits Ieee Transactions On Computers. 67: 1092-1104. DOI: 10.1109/Tc.2018.2807818  0.396
2017 Zhang P, Mills A, Zambreno J, Jones PH. The design and integration of a software configurable and parallelized coprocessor architecture for LQR control Journal of Parallel and Distributed Computing. 106: 121-131. DOI: 10.1016/J.Jpdc.2017.01.028  0.452
2016 Wang X, Jones PH, Zambreno J. A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns Acm Sigarch Computer Architecture News. 43: 76-81. DOI: 10.1145/2927964.2927978  0.431
2016 Nelson C, Townsend KR, Attia OG, Jones PH, Zambreno J. RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing Ieee Transactions On Parallel and Distributed Systems. 27: 3029-3043. DOI: 10.1109/Tpds.2015.2513053  0.322
2015 Townsend KR, Attia OG, Jones PH, Zambreno J. A scalable unsegmented multiport memory for FPGA-based systems International Journal of Reconfigurable Computing. 2015. DOI: 10.1155/2015/826283  0.35
2015 Attia OG, Townsend KR, Jones PH, Zambreno J. A reconfigurable architecture for the detection of Strongly Connected Components Acm Transactions On Reconfigurable Technology and Systems. 9. DOI: 10.1145/2807700  0.394
2015 Johnson T, Roggow D, Jones PH, Zambreno J. An FPGA Architecture for the Recovery of WPA/WPA2 Keys Journal of Circuits, Systems, and Computers. 24: 1550105. DOI: 10.1142/S0218126615501054  0.461
2014 Chetan Kumar NG, Vyas S, Cytron RK, Gill CD, Zambreno J, Jones PH. Hardware-software architecture for priority queue management in real-time and embedded systems International Journal of Embedded Systems. 6: 319-334. DOI: 10.1504/Ijes.2014.064997  0.473
2014 Pande A, Chen S, Mohapatra P, Zambreno J. Hardware Architecture for Video Authentication Using Sensor Pattern Noise Ieee Transactions On Circuits and Systems For Video Technology. 24: 157-167. DOI: 10.1109/Tcsvt.2013.2276869  0.428
2014 Vyas S, Chetan Kumar NG, Zambreno J, Gill C, Cytron R, Jones P. An FPGA-based plant-on-chip platform for cyber-physical system analysis Ieee Embedded Systems Letters. 6: 4-7. DOI: 10.1109/Les.2013.2262107  0.427
2013 Vyas S, Gupte A, Gill CD, Cytron RK, Zambreno J, Jones PH. Hardware architectural support for control systems and sensor processing Transactions On Embedded Computing Systems. 13. DOI: 10.1145/2514641.2514643  0.382
2013 Pande A, Mohapatra P, Zambreno J. Securing Multimedia Content Using Joint Compression and Encryption Ieee Multimedia. 20: 50-61. DOI: 10.1109/Mmul.2012.29  0.437
2013 Pande A, Zambreno J. A chaotic encryption scheme for real-time embedded systems: Design and implementation Telecommunication Systems. 52: 551-561. DOI: 10.1007/S11235-011-9460-1  0.421
2012 Pande A, Zambreno J. Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2146417.2146423  0.452
2012 Sun S, Monga M, Jones PH, Zambreno J. An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs Ieee Transactions On Circuits and Systems. 59: 113-123. DOI: 10.1109/Tcsi.2011.2161389  0.419
2012 Pande A, Zambreno J, Mohapatra P. Comments on ''arithmetic coding as a non-linear dynamical system'' Communications in Nonlinear Science and Numerical Simulation. 17: 4536-4543. DOI: 10.1016/J.Cnsns.2012.06.006  0.348
2012 Pande A, Zambreno J. The secure wavelet transform Journal of Real-Time Image Processing. 7: 131-142. DOI: 10.1007/S11554-010-0165-6  0.465
2011 Sun S, Zambreno J. Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining Ieee Transactions On Parallel and Distributed Systems. 22: 1497-1505. DOI: 10.1109/Tpds.2011.34  0.397
2011 Baumgarten A, Steffen M, Clausman M, Zambreno J. A case study in hardware Trojan design and implementation International Journal of Information Security. 10: 1-14. DOI: 10.1007/S10207-010-0115-0  0.371
2011 Pande A, Zambreno J. Efficient mapping and acceleration of AES on custom multi-core architectures Concurrency Computation Practice and Experience. 23: 372-389. DOI: 10.1002/Cpe.1647  0.424
2010 Pande A, Zambreno J. Reconfigurable hardware implementation of a modified chaotic filter bank scheme International Journal of Embedded Systems. 4: 248-258. DOI: 10.1504/Ijes.2010.039028  0.386
2010 Baumgarten A, Tyagi A, Zambreno J. Preventing IC Piracy Using Reconfigurable Logic Barriers Ieee Design & Test of Computers. 27: 66-75. DOI: 10.1109/Mdt.2010.24  0.317
2009 Sun S, Yan Z, Zambreno J. Demonstrable differential power analysis attacks on real-world FPGA-based embedded systems Computer-Aided Engineering. 16: 119-130. DOI: 10.3233/Ica-2009-0309  0.404
2009 Bloom G, Narahari B, Simha R, Zambreno J. Providing secure execution environments with a last line of defense against Trojan circuit attacks Computers and Security. 28: 660-669. DOI: 10.1016/J.Cose.2009.03.002  0.425
2008 Das A, Nguyen D, Zambreno J, Memik G, Choudhary A. An FPGA-based network intrusion detection architecture Ieee Transactions On Information Forensics and Security. 3: 118-132. DOI: 10.1109/Tifs.2007.916288  0.604
2008 Das A, Ozdemir S, Memik G, Zambreno J, Choudhary A. Microarchitectures for managing chip revenues under process variations Ieee Computer Architecture Letters. 7: 5-8. DOI: 10.1109/L-Ca.2008.3  0.574
2008 Sathre J, Zambreno J. Automated software attack recovery using rollback and huddle Design Automation For Embedded Systems. 12: 243-260. DOI: 10.1007/S10617-008-9020-4  0.488
2005 Zambreno J, Choudhary A, Simha R, Narahari B, Memon N. SAFE-OPS: An approach to embedded software security Acm Transactions On Embedded Computing Systems (Tecs). 4: 189-210. DOI: 10.1145/1053271.1053279  0.565
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