Trevor N. Mudge - US grants

This research addresses the major architectural and technological trade-offs inherent in multiple-bus computer systems. The focus will be on two main issues: (1) analysis of the basic architectural features of multiple-bus systems; and (2) development of new performance models for such systems. Technology-dependent analytical models that account for the loading, crosspoint control, and access arbitration in shared- memory architectures are being developed. The recently introduced crosspoint cache will be further explored. Together with an address-trace generation, parameters are provided in the development and evaluation of a new semi-Markov bus performance model. Efficient reconfiguration strategies for systems with bus failures are also integrated into the performance models.

Sakallah This research is on the temporal modeling of latch- controlled synchronous digital systems. The use of level- sensitive latches, as opposed to edge-triggered flip-flops, has become quite common in recent years because latches are easily implemented in MOS VLSI, the leading technology for building digital systems. A consistent theoretical framework for describing the timing constraints which must be satisfied by such systems for proper operation is being developed. This framework is being used to develop efficient algorithms for timing verification and optimal clocking. Both of these problems require the solution of large linear programs (LPs). The special structures of these LPs will be utilized to reduce the solution time so that the algorithms can be used in an interactive design environment. The practical significance of this framework and associated algorithms is being assessed experimentally on actual industrial VLSI designs.

This award is for the purchase of a Tektronix DAS 9200 logic analyzer and DECstation 5000 workstation to support research and development of a high performance GaAs microcomputer system, implementation and evaluation of a distributed real-time fault-tolerant system, and studies on the interaction between operating systems and computer architecture. Microcomputer systems have enjoyed a performance increase of 100% to 200% every three years. Much of this increase of performance is due to the growth in chip integration. The University of Michigan plans to develop a prototype "micro- supercomputer" that will achieve the best of both the supercomputer and microprocessor traditions by using a high- speed technology that has good integration density, and a state-of-the-art packaging technology to prevent chip- crossings from dominating the overall speed of the system.//

Mudge This project supports a rapid prototyping facility that allows researchers in computer architecture to prototype their designs and obtain accurate performance measurements. The equipment in the facility are available nationally over the Internet, and staff are employed by the facility to assist remote users in prototyping their designs and in connecting custom hardware to the facility's equipment. The major component of the facility is a Quickturn Enterprise System that can prototype logic netlists of a target system in a network of FPGA's. It can emulate the target with a slowdown of only a few hundredfold, which is fast enough to exercise the design with significant benchmarks, test functionality, and take performance measurements. A built-in logic analyzer and stimulus generator permit detailed performance measurement and functional testing.

This research is on a timing verification and optimization framework for designing an entire digital system (e.g. a microprocessor). The research builds on a widely used model for synchronous timing analysis and an efficient method for estimating gate and wire delays. The model is being extended to include relevant functional information in order to enhance accuracy. Components of the framework are: design decomposition to isolate critical elements; a path delay calculator; algorithms for finding synchronizer components; clock analysis algorithms; a symbolic sequential timing verification component; a hybrid timing-logic simulator; and design optimizers.

ABSTRACT

Title: Research Into Code compression
PI: Trevor Mudge, University of Michigan

The research examines the problem of reducing the size of programs. This is termed "code compression." The size of programs can adversely affect the performance of a computer in several ways, but until recently, code
compression has been targeted at low cost systems, where chip size and thus cost is at a premium. Reducing chip size suggests that the code compression techniques may also reduce power consumption, because the power consumed by a chip is related, among other things to its area. Furthermore, earlier studies by the Principal Investigator have shown that compression can improve the memory system efficiency and, as a result improve system performance. There are three directions being pursued in this research: 1) to explore the use of code compression to reduce chip size and cost; 2) to explore the use of code compression to reduce power; and 3) to explore the use of code compression to improve performance. The impact of this work is expected to be reduced chip size and power consumption for the same or better performance. The research leverages tools that were created by the Principal Investigator in prior code compression work.

Abstract
Researchers at The University of Michigan, Arizona State University, and Princeton University
will, during the next four years, explore core technologies for the next generation of computer
systems, suitable for untethered pervasive computing. The requirements of the computing sub-strate
in such devices is mind boggling, and so we have collected our research under the title of
Mobile Supercomputing. We believe this phrase captures the need for the order-of-magnitude
increase in performance need by such systems, while maintaining the minimal power budget that
is essential for mobile computing systems. The core technologies are a synergistic combination of
novel co-design and circuit techniques that integrate into a generic platform architecture for
mobile supercomputing.

The significance of this work for the user of tomorrows pervasive mobile computers will be that
that they will provide a highly versatile light-weight computing and communication device with
hands-free user interfaces such as speech recognition, gesture recognition, facial expression, and
streaming voice/video. This will allow the user to perform stand alone computing, communicate
with others in a number of ways, and provide a sophisticated portal to the internet and other
remote computing resources.

This project is to create the pilot for a pervasive computing facility through all areas of a building, including offices, lecture rooms, hallways, and common areas. The pilot will include a heterogeneous space comprising a significant fraction of a building. In this area, there will be a sensor network, capable of tracking hundreds of mobile clients to a granularity of less than 10 feet as they move freely through the building.

Research Impact:

The proposed facility will be used to advance research at a number of levels, from low-level system building to human-oriented applications. There are three main avenues through which this facility will advance research. First, it will be used to understand issues of scale and heterogeneity in the deployment of novel technologies that have been developed at the University of Michigan, ranging from nano-sensors to cognitive orthotics. Second, the mobility traces collected from the consistent use of this facility will lead both to the creation of new benchmarks for mobile system/algorithm designers as well as to superior building design. Third, given that the system requires the tracking of many building occupants, there will be an opportunity to study interesting issues of privacy and the manner in which individuals exercise choice.

Broader Impact:

At the University of Michigan, there are a number of on-going and planned research efforts that leverage sensor technology and/or mobile environments. Access to a large pervasive computing facility will be crucial to testing these technologies at scale and taking them to the next stage towards commercialization. More important, the pervasive computing facility will be deployed in the building in which the project team works everyday, along with many colleagues and students. This gives rise to a unique "living laboratory" experience through which to appreciate both the technological and social effects of the pervasive computing facility.

Over the next five to ten years, the deployment of untethered/pervasive computers will increase rapidly. The prime example is the cell phone, but the emergence of many new classes of such devices is expected. These devices will improve on the cell phone by moving advanced functionality, such as always-on Internet access, high-definition streaming video, and human-centric interfaces with voice recognition. One of the key ingredients to pervasive computing is wireless communication. Mobile devices must be able to seamlessly interface to whatever communication services are available as they are moved from location to location, such as different cellular networks and wireless local area networks. Software defined radio (SDR) promises to deliver flexible solutions by implementing wireless protocols wholly in software. SDR executing on programmable hardware substrates facilitates the inter-operability, flexibility, and support for new features that pervasive computing requires. Further, SDR prevents getting locked into fixed and outdated standards that traditional hardware-centric solutions are often faced with. This project focuses on hardware and software innovations to create platforms for SDR that are both programmable and scalable to the projected bandwidth requirements for the next ten years. Innovation in a single direction is not sufficient to accomplish these goals. Rather, a multi-layered approach, consisting of innovation hardware, compiler, and algorithms, is used. Across these three dimensions, this project will develop general techniques for decomposing signal processing algorithms to exploit coarse-grained parallelism, compiler technologies orchestrating the execution of communicating sequential tasks on multicore computing systems, and platform-wide power-aware architectural techniques for supporting SDR on mobile computing devices.

Energy efficiency is rapidly becoming a key constraint in the design of enterprise systems. By 2011, yearly data center energy consumption in the United States is projected to grow to over 100 billion kWh at cost of $7.4 billion. As much as 40% of this energy is consumed by DRAM and disks.
Portable consumer devices, where battery life has long been a key concern, instead use faster and more energy-efficient Flash storage. Flash is non-volatile, has near-zero standby power draw, and each Flash read requires 30x less power than a DRAM read and three orders-of-magnitude less power than a disk access. Moreover, Flash provides far lower access latency and higher bandwidth than disks, approaching DRAM performance levels. Enterprise storage vendors have recently announced products that replace traditional disks with high-capacity Flash solid-state disks (SSDs). However, because they are accessed through interfaces optimized for legacy rotating disks, SSDs fail to fully-exploit the low latency and high bandwidth Flash can provide. Furthermore, replacing conventional disks with SSDs does not address the growing power consumption of severs'
DRAM. In this project, we examine further opportunities, beyond SSDs, to save energy with Flash in enterprise systems by integrating Flash throughout the servers' storage and memory hierarchies. The long term goal of our research--to improve data center energy efficiency--has the potential to drastically reduce the carbon footprint of data centers and the need for additional power generation capacity.

Many critical workloads today, such as web-hosted services, are limited not by raw CPU processing power but by interactions between the CPU cores, the memory system, I/O devices such as disks and network interfaces, and the complex software (applications, middleware, operating systems, virtual machines) that ties all these components together. To improve the efficiency of these workloads and systems, designers and developers need tools to identify the bottlenecks, so that they can address them. However, existing performance analysis tools, such as software profilers, cannot account for hardware bottlenecks or for situations where software overheads are hidden due to overlap with other operations.

As computer systems become ever more complex networked aggregations of software and hardware from multiple vendors, the ability to isolate and address inefficiencies that reduce throughput and waste energy is daunting. The goal of the project is to address this problem by developing an analysis methodology and tool set that identifies true bottlenecks in complex systems spanning multiple software and hardware layers executing concurrently across multiple CPU cores and dedicated hardware devices. This research utilizes critical-path analysis to not only identify bottlenecks but also quantify their contribution and estimate the speedup obtainable if a particular set of bottlenecks is removed or reduced. Ultimately, this research will lead to qualitative performance improvements in software and hardware system designs as the methodology and tools produced aid designers and developers in focusing their efforts on removing the true bottlenecks.

The project involves both graduate and undergraduate students as researchers. The results will be fed into appropriate courses, including one on parallel architectures. The material and slides for this course will be made available over the web.

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).

Moore?s law promises consistent increasing transistor densities for the foreseeable future. However, device scaling no longer delivers the energy gains that drove the semiconductor growth of the past several decades. This has created a design paradox: more gates can now fit on a die, but cannot actually be used due to strict power limits. In this project, we will address this energy crisis through the universal application of ?near-threshold computing? (NTC), where devices operate at or near their threshold voltage to obtain 10X or higher energy efficiency improvements. To accomplish this we focus on three key challenges that to date have kept low voltage operation from widespread use: 1) 10X loss in performance, 2) 5X increase in performance variation, and 3) 5 orders of magnitude increase in functional failure. We present a synergistic approach combining methods from algorithm and architecture levels to the circuit and technology levels. We will demonstrate NTC for applications that range from sensor-based platforms which critically depend on ultra-low power (≤mW) and reduced form factor (mm3) to unlock new applications, to high-performance platforms in large data-centers, which dissipate so much power that they require co-location near dedicated cooling facilities. Our end goal is to reduce national energy consumption and environmental impact by providing dramatic gains in energy efficiency while also opening up new application areas in health care by providing for in situ monitoring of biological functions with minimum intervention.

This research aims to overcome the extreme challenges that need to be solved to realize a 1000-core (kilocore) processor. Processors with tens of cores are already in commercial products today. A kilocore processor could take us into the era of Server-on-Chip and Supercomputer-on-Chip. On-chip network is the medium through which two nodes in a processor can communicate, and therefore constitutes the backbone of a kilocore processor. Unfortunately, current on-chip network solutions are inadequate as they do not scale in terms of both power and performance beyond a few tens of cores. To reach the ambitious design goal of 1000+ cores with realistic power budgets, the interconnect technology needs to be at least 15 times more power efficient while providing at least the same level of throughput-per-core as today.

This project investigates three interrelated solutions to meet the above challenge in an evolutionary manner: (1) Developing a low-power and energy-proportional interconnect architecture that employs a larger number of narrower networks, (2) Using high-radix Swizzle-Switches as the building blocks for interconnecting the multiple networks, and (3) Re-designing network architecture with multiple networks and Swizzle-Switches using 3D integration with Through-Silicon-Vias to achieve scalability beyond 1000 cores. This project will demonstrate the feasibility of kilocore processors. If such processors can be built, they could have a tremendous impact on future exascale systems such as cloud computing servers and HPC systems that have many applications including drug discovery, defense, information analysis, and social networking.