David Blaauw - US grants

As CMOS technology enters the nanometer-regime, one of the most fundamental challenges will result from the loss of predictability of design behavior due to both variations during manufacturing and interferences between components during normal operation. As features on the die continue to shrink, control of the physical parameters, such as the feature size of transistors, their doping levels, and oxide thickness, will become increasingly difficult to control, resulting in dramatic increased uncertainty in the electrical characteristics of individual devices. Also, the close proximity of devices to each other will give rise to significant interference from elements surrounding a device, due to inductive and capacitive coupling, and due to environmental factors, such as power supply and temperature fluctuations. The increase in the number of uncertainties, as well as their severity will result in a general loss of predictability in nanometer-CMOS design and will threaten the ability to produce robust designs.

In this project, we are developing a statistical framework for analysis and optimization of system performance, power, and functional integrity, as well as their newly emerging trade-offs in nanometer design. In the presence of variations due to process fluctuations and environmental interferences, signals are inherently stochastic as are the basic measures of design quality, such as delay and power. The research is therefore investigating the development of stochastic models for performance metrics that capture their dependence on the various sources of uncertainty. The new design methodology will focus on robustness as a new measure of design quality, including delay, power consumption and measures of functional integrity, and will allow these design objectives to be constrained at prescribed levels of confidence. Furthermore, the research team is considering new methods for simultaneous optimization of performance, energy, and functional integrity that effectively exploit new trade-offs and interactions between these objectives in nanometer design.

Abstract
Researchers at The University of Michigan, Arizona State University, and Princeton University
will, during the next four years, explore core technologies for the next generation of computer
systems, suitable for untethered pervasive computing. The requirements of the computing sub-strate
in such devices is mind boggling, and so we have collected our research under the title of
Mobile Supercomputing. We believe this phrase captures the need for the order-of-magnitude
increase in performance need by such systems, while maintaining the minimal power budget that
is essential for mobile computing systems. The core technologies are a synergistic combination of
novel co-design and circuit techniques that integrate into a generic platform architecture for
mobile supercomputing.

The significance of this work for the user of tomorrows pervasive mobile computers will be that
that they will provide a highly versatile light-weight computing and communication device with
hands-free user interfaces such as speech recognition, gesture recognition, facial expression, and
streaming voice/video. This will allow the user to perform stand alone computing, communicate
with others in a number of ways, and provide a sophisticated portal to the internet and other
remote computing resources.

Abstract

In the not too distant future, semiconductor designs are expected to integrate billions of transistors on a single chip and will operate at frequencies in excess of 10GHz. This dramatic progress will introduce unforeseen challenges and will require dramatic changes of the tools and methods used to design highperformance processors. With high operating frequencies, accurate performance verification of the design will be come paramount. At the same time, noise in the design will rise to dramatic new levels due to the coupling between closely spaced devices on the same die. High noise levels will impact the performance by slowing down the critical delay paths in a circuit and will therefore threaten the achievable operating frequencies. We therefore propose new methods for the analysis of processor performance in the presence of high-noise levels. Furthermore, we intend to develop new methods for performance optimization in noise dominated circuit environments for future high-performance processor and systems-on-chip designs.

PROPOSAL NO: 0429700
INSTITUTION: University of Michigan Ann Arbor
PRINCIPAL INVESTIGATOR: Flynn, Michael
TITLE: Collaborative Research: Communication Fabrics for the Globally
Asynchronous Network-on-chip Era


Abstract
This research addresses the critical problems of design complexity, power consumption, and reliable, efficient signaling that now impede progress in digital integrated systems. Continuing progress in digital integration and performance is vital to the continued development of information technology (IT). As the number of transistors on an integrated circuit reaches the 1 billion mark, both the current monolithic design style and the globally synchronous clocking and signaling paradigm will fail. The exponential growth in complexity is causing explosions in both design time and cost. In order to achieve the social and economic IT goals of the NSF, dramatic improvements must be made in the processing power, integration, and energy efficiency of digital integrated circuits. Although transistor feature size is expected to continue to scale for at least the next fifteen years, power consumption, global signaling, and clocking have become critical problems that now prevent improvements in system performance, efficiency, and integration. The globally asynchronous locally synchronous (GALS) scheme within a network-on-chip paradigm is a good long-term solution, but this communications-centric methodology can only succeed with a fundamentally new approach to on-chip communication. The investigators are exploring new schemes for global and local communication that take advantage of the capabilities of nanometer CMOS.
The communications-centric network-on-chip approach places a far greater burden on on-chip communication. Robust communication between asynchronous network components is difficult using present techniques. Modern techniques will also be stretched to their limits to provide adequate local communication. The investigators are developing a new framework for communication across a modular IC, at both the global (full chip) and local (intra-module) levels. Global communication between asynchronous modules is achieved with robust and power efficient serial links instead of traditional parallel buses. This research also concerns new circuit and interconnect structures for local (intra-module) communications and clocking. At a lower level, wires themselves are studied and optimized for both local and global signaling.

Proposal No: 0811612
PI: Sylvester, Dennis
Title: CPA-DA: Probabilistic wearout in Nanoscale CMOS: analysis, monitoring and optimization
Institution: University of Michigan Ann Arbor

ABSTRACT
The PIs propose the development of computer-aided design tools and circuit design techniques to analyze, monitor, and improve the reliability of integrated circuits in extremely scaled CMOS (i.e., sub-45nm) with significant levels of variability present. The desired outcome is a cohesive approach that improves chip lifetimes via both better estimation at design time (leading to reduced design margining, and therefore design times and costs) and circuit-based techniques that enable post-fabrication monitoring and improvement of robustness during the lifetime of a given die. The key components of this work include: 1) a tool that statistically determines expected chip-level reliability, 2) a theoretically rigorous approach that uses a small number of post-silicon measurements on a wafer to improve the reliability/performance characteristics of a larger set of chips, 3) new ultra-compact on-chip sensors to monitor reliability mechanisms with low overhead and compatibility with modern design methodologies, 4) a novel indirect measurement scheme based on the quiescent current draw of a chip to monitor for wearout, 5) design styles to combat very high intrinsic failure rates (e.g., 1 in 1000 devices fail).

The proposed strategy to improve reliability in highly variable nanoscale CMOS will facilitate sustained improvement in the performance and robustness of integrated circuits - a necessary condition for the continued evolution of semiconductor and information technology. In particular, higher functional and parametric yields will enable lower costs, which will largely benefit cost-constrained markets such as wireless/mobile. The impact of this work will be enhanced by leveraging promising undergraduate researchers, through improvements in curriculum, and through industrial interaction via class project mentoring. At the graduate level, this research will involve several students pursuing doctoral and master?s degrees, training them directly to conduct research in this area. The knowledge developed under the proposed research will be incorporated in VLSI CAD and circuits courses at both the undergraduate and graduate levels. Seminars and tutorials presented at the departmental level, at conferences, and at other universities will play an important role in disseminating the knowledge gained from this research, along with conventional publication in top journals and international conferences.

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).

Moore?s law promises consistent increasing transistor densities for the foreseeable future. However, device scaling no longer delivers the energy gains that drove the semiconductor growth of the past several decades. This has created a design paradox: more gates can now fit on a die, but cannot actually be used due to strict power limits. In this project, we will address this energy crisis through the universal application of ?near-threshold computing? (NTC), where devices operate at or near their threshold voltage to obtain 10X or higher energy efficiency improvements. To accomplish this we focus on three key challenges that to date have kept low voltage operation from widespread use: 1) 10X loss in performance, 2) 5X increase in performance variation, and 3) 5 orders of magnitude increase in functional failure. We present a synergistic approach combining methods from algorithm and architecture levels to the circuit and technology levels. We will demonstrate NTC for applications that range from sensor-based platforms which critically depend on ultra-low power (≤mW) and reduced form factor (mm3) to unlock new applications, to high-performance platforms in large data-centers, which dissipate so much power that they require co-location near dedicated cooling facilities. Our end goal is to reduce national energy consumption and environmental impact by providing dramatic gains in energy efficiency while also opening up new application areas in health care by providing for in situ monitoring of biological functions with minimum intervention.

Applications of wireless sensor nodes are evolving at a previously unimaginable rate. But current technology is limited because devices are bulky - measuring one cubic centimeter or more - and hampered by short lifetimes. This project is producing a one cubic millimeter sensor node. This ultra-miniaturized device is a complete sensing platform that includes transducers (for imaging, temperature sensing and other signal detection), wireless communication, a high accuracy timer, processor, memory, a battery and energy harvesting that provides the node with an extended lifetime.

The central challenge in reducing the form factor for sensor nodes is to reduce power consumption and
densely package discrete components (crystals, inductors, etc.). To this end, this team's innovations involve research and development of:

1. A novel processor that operates at a supply voltage near the threshold voltage of the transistors for optimal energy consumption.
2. A new ultra-low-leakage memory system.
3. An Ultra Wide-Band (UWB) transmitter and receiver that can communicate with other nodes over a distance of three meters with an integrated antenna.
4. A 100pW timer that is temperature compensated and designed for reduced jitter to allow accurate synchronization between sensor nodes and enable short, low energy radio communication windows.
5. A new CMOS imaging approach capable of ultra-low power motion detection and image-acquisition, and, reconfigurable to act as a solar energy harvesting unit.
6. An energy-aware software development environment to control the node

These PIs implemented early versions of several of these technologies in silicon, demonstrating the potential to package them as sensor nodes. The team's track record of producing ultra-low power circuits, and other sensing components, position them to deliver the needed 1000× form factor reduction. This research team will assemble and package 100 first- and second-generation of these sensor node platforms and disseminate them to the broader community for trials in a wide range of uses.

The development of cubic-millimeter sensor nodes will enable applications that have long been envisioned but were unachievable. For example, sensory skins could cover surfaces with a dense deployment of nodes that monitor the properties of the manifold itself or its surroundings. Implantable intelligence can enable deeply embedded physical and biological processes, e.g., malignant tumor growth monitoring or intra-ocular pressure sensing to determine the risk for retinal detachment. Applications such as these, and a myriad of other "Thinking and Linking" applications, can give everyday objects sensing, computing, communication, and tracking ability, allowing, for example, research ranging from the social network patterns of small insects to asset tracking in dynamic environments like hospitals. By shrinking sensor node size to one cubic millimeter, with potentially perpetual lifetime, the concept of "smart dust" can be taken from fiction to reality.

By disseminating the first generation of these sensors to members of the sensor network community, this project will dramatically accelerate the adoption of cubic-millimeter-class computing devices. This will have immediate impact on a wide array of research programs for intelligently sensing, tracking, measuring and optimizing physical processes. This research in turn will have a fundamental and long term impact on a diverse set of applications with critical societal import, ranging from energy conservation, environmental quality management, and health care.

Microprocessors form the heart of most electronic systems that pervade our daily life and they are responsible for the bulk of the power consumption of those electronics. In this research, the PIs propose a promising method to significantly reduce that power consumption, using an approach called Razor. One of the issues with modern chips manufactured using silicon semi-conductor processes is that the performance of the electronic components (such as transistors, gate, etc) on these chips has become very unpredictable in terms of their computational speed. This means some chips will run fast while others will run slow. Currently, we address this performance uncertainty by operating all chips at a slow speed that is considered safe for all possible chips. However, this is hugely wasteful for most chips which can operate at a much faster performance. We harness the performance margin of these chips by lowering their operating voltage, such that they still meet the same safe performance constraint, but operate significantly more energy efficiently. It has been demonstrated that this approach can save as much as 50% of the power consumption of an electronic circuit. The proposal suggests new ways for the chip to automatically determine its lowest possible operating voltage while still meeting the needed performance. It does so by progressively lowering the supply voltage till the chip start to fail. These failures are then detected and corrected and tell the voltage control that it has reached the limit of voltage reduction. In this proposal, the PIs outline a new method to perform this error detection and correction in a more efficient manner.

The proposed methods, if successful and transferred to industry, could significantly reduce energy consumption of processors and other electronic circuits. The significantly larger energy efficiency of the proposed techniques could bring about a number societal benefits. These technique will enable more effective usage of energy for electronic circuits. Power consumption of electronic circuits (computers, handhelds, servers farms etc.) is currently the fastest growing component of the nation?s overall energy demand. Hence, reducing power consumption of electronics is a critical concern for energy policy and could reduce our dependence on oil and other non-renewable energy sources. In addition, the proposed method will address a critical need to design circuits that are immune to the increasing uncertainty in chips as we scale the silicon technology further. This could play an important role in extending Moore's law of scaling and have significant benefits for the semiconductor industry and the nation?s economy. As part of this research, the PIs will expand our recent practices of engaging with high school students through lab demonstrations and tours to prepare these students for low power computing.

? DESCRIPTION (provided by applicant): Technologies to non-invasively, continuously measure biochemical, metabolic, and biophysical changes in living tissues and organs have the capability to transform medical research and health care. Imaging and biopsies currently are the predominant methods to analyze disease status. Since these approaches provide only a limited number of snapshots over extended periods of time, researchers and clinicians may miss critical changes in physiology and disease status. We propose to overcome this fundamental medical problem by developing a new generation of ultra-low power, wireless, implantable, mm- scale biosensors for real-time, continuous monitoring of interstitial fluid pressure or extracellular pH n tumors. Elevated interstitial fluid pressure and acidic pH are characteristic features of almost al solid tumors, and prior studies suggest that changes in these parameters may be sensitive, early biomarkers for treatment response in many different malignancies. We will design sensors for percutaneous insertion into a tumor before starting chemotherapy. Sensors will remain in place over the multi-week course of treatment, continuously recording pressure or extracellular pH for periodic wireless transmission to an external readout device. We expect changes in interstitial pressure or pH in tumors will occur before alterations in tumor size and at least as soon as changes in tumor metabolism measured by clinical positron emission tomography (PET) imaging. To meet the challenge of extended tumor monitoring, we will advance our biosensor technology in four new areas: 1) through-tissue energy harvesting of infrared (IR) radiation, which will enable implantable devices to operate essentially perpetually in a non-invasive manner; 2) a new self-starting voltage converter to allow system charging after encapsulation is completed, facilitating high quality sealing of the electronics from the in vivo environment; 3) new pressure sensing and pH readout circuits for stable readout under unregulated sensor power supplies; and 4) pre-clinical studies to determine response to therapy in a mouse model of breast cancer. The combined expertise of our multi-disciplinary team uniquely positions us to develop transformative new biosensor technology for continuous monitoring of tumor environments, which will advance understanding of cancer biology and ultimately improve personalized cancer therapy. RELEVANCE (See instructions): We will develop mm-scale electronic biosensors that can be implanted into a tumor to continuously monitor response to several weeks of cancer therapy. By measuring changes in fluid pressure or acid-base balance in a tumor, we expect to detect success or failure of treatment within days of beginning chemotherapy. We expect this biosensor technology ultimately will provide a cheaper, more accurate method to determine efficacy of cancer therapy, allowing doctors to tailor chemotherapy protocols to individual patients and increase patients cured of cancer.

Project Summary / Abstract In this research proposal, we present a new approach for recording and transmitting neural signals at the level of single neurons using micron-scale distributed implants referred to as micro-probes (mProbes). Fully wireless and 100x100um in size, standalone mProbes are injected into the brain at nearly unlimited locations in the sub-arachnoid space. To enable wireless power and communication, we utilize a two-step approach with a repeater in the epidural space, which communicates wirelessly with an outside receiver through a conventional inductive link, and a novel near- infra-red (NIR) based link from the repeater to the mProbes for wireless powering and two-way communication. The system is highly scalable and allows tens-of-thousands of mProbes to be inserted in the brain on a tight 100um pitch. The repeaters collect the mProbe neural recordings in a manner that preserves precise neural signal timing and spatial resolution via code- and space-division multiple access (CSDMA). Each repeater can accommodate up to 1,500 mProbes and an array of hundreds of repeaters can be deployed to cover a large area and enable 10s to 100s of thousands of recording sites. Key advantages of the proposed approach are: 1) NIR transmitters and receivers (LEDs and PV diodes) can scale to um size while maintaining efficiency, unlike RF antennas and ultrasound transducers. 2) By enabling fully wireless power and communication links we achieve mechanical isolation of the implanted probe which reduces tissue damage near the probe shank from long-term brain micro-motion. 3) Elimination of wires that traditionally connect the probe to electronics reduces implant complexity and risk of complications such as infection and cerebrospinal leakage.

Early pathogen detection and disease diagnosis is key to preventing the exponential spread of infectious diseases such as COVID-19. If not detected and contained early, the pathogen not only affects local communities but can cross national and international borders to become a global pandemic. Existing approaches for early pathogen detection can delay diagnosis during a pandemic. These identify regions of interest specific to a pathogen type/sub-type and amplify these regions in target specimens (if present), making them inapplicable to unknown pathogens. Another limitation is the dependence on the design of primer chemistry, which is a complex, error-prone, and time-consuming process that can delay pathogen detection in the early stages of a pandemic. Further, it is also important to track the accumulation of novel mutations to identify disease hotspots, monitor virus evolution, guide immunization efforts, and inform public healthcare plans. It has been estimated that RNA coronaviruses such as
SARS-CoV-2 can accumulate 30 substitutions/year. The proposed approach will enable design for fast and accurate whole-genome sequencing (WGS) analysis pipelines for strain typing and phylogenetic classification. The proposed real-time diagnosis pipeline can potentially serve as a "digital sniffer" and be used to detect potential outbreaks early.

The researchers propose to build real-time diagnosis pipelines for early pathogen detection using the portable Oxford Nanopore Sequencer MinION. The read-until functionality of the sequencer can be used to adaptively target sequencing towards genome regions with low-coverage and accelerate whole-genome sequencing of unknown pathogens. The ultimate goal of this project is to develop point-of-care mobile rapid pathogen diagnosis and analysis. This will be realized by developing novel hardware-acceleration techniques and algorithms for quick classification of viral/bacterial pathogens, followed by strain detection and epidemiology analysis. The proposed techniques include hardware-software co-design for squiggle-space classification algorithms, refined indexes, exploiting real-time feedback feature of MinION sequencing devices (read-until and run-until), and variant calling to achieve rapid analysis. The project will also explore direct RNA sequencing without reserve transcriptase step to reduce library-preparation time.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.