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Edward J. Mccluskey

Affiliations: 
Computer Science Stanford University, Palo Alto, CA 
Google:
"Edward Joseph McCluskey" OR "Edward J McCluskey"
Bio:

McCluskey, Edward Joseph Algebraic minimization and the design of two-terminal contact networks Thesis (Sc.D.) Massachusetts Institute of Technology. Dept. of Electrical Engineering, 1956.

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Parents

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Samuel H. Caldwell grad student 1956 MIT
 (Algebraic minimization and the design of two-terminal contact networks)

Children

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Janusz A. (John) Brzozowski grad student 1962 Princeton (E-Tree)
Samuel Henry Fuller grad student 1972 Stanford
Daniel P. Siewiorek grad student 1972 Stanford
Jacob A. Abraham grad student 1974 Stanford (E-Tree)
Joseph L. A. Hughes grad student 1986 Stanford (E-Tree)
Nur A. Touba grad student 1996 Stanford (E-Tree)
Wei-Je Huang grad student 2001 Stanford
Nahmsuk Oh grad student 2001 Stanford
Philip P. Shirvani grad student 2001 Stanford
Chien-Mo Li grad student 2002 Stanford
Shu-Yi Yu grad student 2002 Stanford
Mehdi Baradaran Tahoori grad student 2003 Stanford
Ahmad A. Al-Yamani grad student 2004 Stanford
Erik Chmelar grad student 2004 Stanford
Kyoung Y. Cho grad student 2008 Stanford
Francois-Fabien Ferhani grad student 2008 Stanford
Donghwi Lee grad student 2008 Stanford
Intaik Park grad student 2009 Stanford
Jackwang Lee grad student 2010 Stanford

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Publications

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Al-Yamani AA, McCluskey EJ. (2010) Test set compression through alternation between deterministic and pseudorandom test patterns Journal of Electronic Testing: Theory and Applications (Jetta). 26: 513-521
Lee J, Park I, McCluskey EJ. (2008) Error sequence analysis Proceedings of the Ieee Vlsi Test Symposium. 255-260
Ferhani FF, Saxena NR, McCluskey EJ, et al. (2008) How many test patterns are useless? Proceedings of the Ieee Vlsi Test Symposium. 23-28
Park I, Lee D, Chmelar E, et al. (2008) Inconsistent fails due to limited tester timing accuracy Proceedings of the Ieee Vlsi Test Symposium. 47-52
Park I, McCluskey EJ. (2008) Launch-on-shift-capture transition tests Proceedings - International Test Conference
Cho KY, Mitra S, McCluskey EJ. (2008) California scan architecture for high quality and low power testing Proceedings - International Test Conference
Cho KY, McCluskey EJ. (2007) Test set reordering using the gate exhaustive test metric Proceedings of the Ieee Vlsi Test Symposium. 199-204
Ferhani FF, McCluskey EJ. (2007) Classifying bad chips and ordering test sets Proceedings - International Test Conference
Al-Yamani AA, McCluskey EJ. (2005) Test chip experimental results on high-level structural test Acm Transactions On Design Automation of Electronic Systems. 10: 690-701
Park I, Al-Yamani A, McCluskey EJ. (2005) Effective TARO pattern generation Proceedings of the Ieee Vlsi Test Symposium. 161-166
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