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Yale N. Patt - Publications

Affiliations: 
1969-1976 North Carolina State University, Raleigh, NC 
 1976-1988 San Francisco State University, San Francisco, CA, United States 
 1979-1988 University of California, Berkeley, Berkeley, CA, United States 
 1988-1999 University of Michigan, Ann Arbor, Ann Arbor, MI 
 1999- Electrical and Computer Engineering University of Texas at Austin, Austin, Texas, U.S.A. 
Area:
Electronics and Electrical Engineering, Computer Science
Website:
https://www.ece.utexas.edu/people/faculty/yale-patt
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80 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Mutlu O, Belgard R, Gross TR, Jouppi NR, Hennessy JL, Przybylski S, Rowen C, Patt YN, Hwu WW, Melvin SW, Shebanow MC, Yeh T, Wolfe A. Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor Ieee Micro. 36: 70-85. DOI: 10.1109/Mm.2016.66  0.773
2016 Hashemi M, Marr D, Carmean D, Patt YN. Efficient Execution of Bursty Applications Ieee Computer Architecture Letters. 15: 85-88. DOI: 10.1109/Lca.2015.2456013  0.414
2015 Hashemi M, Patt YN. Filtered runahead execution with a runahead buffer Proceedings of the Annual International Symposium On Microarchitecture, Micro. 5: 358-369. DOI: 10.1145/2830772.2830812  0.318
2013 Joao JA, Suleman MA, Mutlu O, Patt YN. Utility-based acceleration of multithreaded applications on asymmetric CMPs Proceedings - International Symposium On Computer Architecture. 154-165. DOI: 10.1145/2485922.2485936  0.58
2012 Ebrahimi E, Lee CJ, Mutlu O, Patt YN. Fairness via source throttling: A configurable and high-performance fairness substrate for multicore memory systems Acm Transactions On Computer Systems. 30. DOI: 10.1145/2166879.2166881  0.634
2012 Joao JA, Suleman MA, Mutlu O, Patt YN. Bottleneck identification and scheduling in multithreaded applications International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 223-234. DOI: 10.1145/2150976.2151001  0.612
2012 Khubaib, Suleman MA, Hashemi M, Wilkerson C, Patt YN. MorphCore: An energy-efficient microarchitecture for high performance ILP and high throughput TLP Proceedings - 2012 Ieee/Acm 45th International Symposium On Microarchitecture, Micro 2012. 305-316. DOI: 10.1109/MICRO.2012.36  0.306
2012 Miftakhutdinov R, Ebrahimi E, Patt YN. Predicting performance impact of DVFS for realistic memory systems Proceedings - 2012 Ieee/Acm 45th International Symposium On Microarchitecture, Micro 2012. 155-165. DOI: 10.1109/MICRO.2012.23  0.364
2011 Ebrahimi E, Miftakhutdinov R, Fallin C, Lee CJ, Joao JA, Mutlu O, Patt YN. Parallel application memory scheduling Proceedings of the Annual International Symposium On Microarchitecture, Micro. 362-373. DOI: 10.1145/2155620.2155663  0.591
2011 Narasiman V, Shebanow M, Lee CJ, Miftakhutdinov R, Mutlu O, Patt YN. Improving GPU performance via large warps and two-level warp scheduling Proceedings of the Annual International Symposium On Microarchitecture, Micro. 308-317. DOI: 10.1145/2155620.2155656  0.618
2011 Ebrahimi E, Lee CJ, Mutlu O, Patt YN. Prefetch-aware shared-resource management for multi-core systems Proceedings - International Symposium On Computer Architecture. 141-152. DOI: 10.1145/2000064.2000081  0.584
2011 Lee CJ, Mutlu O, Narasiman V, Patt YN. Prefetch-aware memory controllers Ieee Transactions On Computers. 60: 1406-1430. DOI: 10.1109/Tc.2010.214  0.645
2011 Patt YN, Mutlu O. Top picks [Guest editors' introduction] Ieee Micro. 31: 6-10. DOI: 10.1109/Mm.2011.16  0.548
2011 Suleman MA, Mutlu O, Joao J, Khubaib K, Patt YN. Data marshaling for multicore systems Ieee Micro. 31: 56-64. DOI: 10.1109/Mm.2010.105  0.572
2010 Suleman MA, Qureshi MK, Khubaib, Patt YN. Feedback-directed pipeline parallelism Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 147-156. DOI: 10.1145/1854273.1854296  0.696
2010 Suleman MA, Mutlu O, Joao JA, Khubaib, Patt YN. Data marshaling for multi-core architectures Proceedings - International Symposium On Computer Architecture. 441-450. DOI: 10.1145/1815961.1816020  0.537
2010 Ebrahimi E, Lee CJ, Mutlu O, Patt YN. Fairness via source throttling: A configurable and high-performance fairness substrate for multi-core memory systems International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 335-346. DOI: 10.1145/1736020.1736058  0.6
2010 Suleman MA, Mutlu O, Qureshi MK, Patt YN. Accelerating critical section execution with asymmetric multicore architectures Ieee Micro. 30: 60-70. DOI: 10.1109/Mm.2010.7  0.755
2010 Ebrahimi E, Lee CJ, Mutlu O, Patt YN. Fairness via source throttling: A configurable and hgh-performance fairness substrate for multi-core memory systems Acm Sigplan Notices. 45: 335-346.  0.368
2009 Lee CJ, Narasiman V, Mutlu O, Patt YN. Improving memory bank-level parallelism in the presence of prefetching Proceedings of the Annual International Symposium On Microarchitecture, Micro. 327-336. DOI: 10.1145/1669112.1669155  0.599
2009 Ebrahimi E, Mutlu O, Lee CJ, Patt YN. Coordinated control of multiple prefetchers in multi-core systems Proceedings of the Annual International Symposium On Microarchitecture, Micro. 316-326. DOI: 10.1145/1669112.1669154  0.574
2009 Joao JA, Mutlu O, Patt YN. Flexible reference-counting-based hardware acceleration for garbage collection Proceedings - International Symposium On Computer Architecture. 418-428. DOI: 10.1145/1555754.1555806  0.601
2009 Kim H, Joao JA, Mutlu O, Lee CJ, Patt YN, Cohn R. Virtual program counter (VPC) prediction: Very low cost indirect branch prediction using conditional branch prediction hardware Ieee Transactions On Computers. 58: 1153-1170. DOI: 10.1109/Tc.2008.227  0.702
2009 Ebrahimi E, Mutlu O, Patt YN. Techniques for bandwidth-efficient prefetching of Linked Data Structures in hybrid prefetching systems Proceedings - International Symposium On High-Performance Computer Architecture. 7-17. DOI: 10.1109/HPCA.2009.4798232  0.638
2009 Suleman MA, Mutlu O, Qureshi MK, Patt YN. Accelerating Critical Section Execution with asymmetric multi-core architectures Acm Sigplan Notices. 44: 253-264.  0.751
2008 Suleman MA, Mutlu O, Qureshi MK, Patt YN. Accelerating critical section execution asymmetricmulti-core architectures International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 253-264. DOI: 10.1145/1508244.1508274  0.75
2008 Suleman MA, Qureshi MK, Patt YN. Feedback-driven threading: Power-efficient and high-performance execution of multi-threaded workloads on CMPs Operating Systems Review (Acm). 42: 277-286. DOI: 10.1145/1346281.1346317  0.727
2008 Joao JA, Mutlu O, Kim H, Agarwal R, Patt YN. Improving the performance of object-oriented languages with dynamic predication of indirect jumps Operating Systems Review (Acm). 42: 80-90. DOI: 10.1145/1346281.1346293  0.604
2008 Qureshi MK, Jaleel A, Patt YN, Steely SC, Emer J. Set-dueling-controlled adaptive insertion for high-performance caching Ieee Micro. 28: 91-98. DOI: 10.1109/Mm.2008.14  0.714
2008 Lee CJ, Mutlu O, Narasiman V, Patt YN. Prefetch-aware DRAM controllers Proceedings of the Annual International Symposium On Microarchitecture, Micro. 200-209. DOI: 10.1109/MICRO.2008.4771791  0.604
2008 Joao JA, Mutlu O, Kim H, Patt YN. Dynamic predication of indirect jumps Ieee Computer Architecture Letters. 7: 1-4. DOI: 10.1109/L-Ca.2007.7  0.703
2008 Tseng F, Patt YN. Achieving out-of-order performance with almost in-order complexity Proceedings - International Symposium On Computer Architecture. 3-12. DOI: 10.1109/ISCA.2008.23  0.603
2008 Chang JL, Kim H, Mutlu O, Patt YN. Performance-aware speculation control using wrong path usefulness prediction Proceedings - International Symposium On High-Performance Computer Architecture. 39-49. DOI: 10.1109/HPCA.2008.4658626  0.615
2007 Kim H, Joao JA, Mutlu O, Lee CJ, Patt YN, Cohn R. VPC prediction: Reducing the cost of indirect branches via hardware-based dynamic devirtualization Proceedings - International Symposium On Computer Architecture. 424-435. DOI: 10.1145/1250662.1250715  0.58
2007 Qureshi MK, Jaleel A, Patt YN, Steely SC, Emer J. Adaptive insertion policies for high performance caching Proceedings - International Symposium On Computer Architecture. 381-391. DOI: 10.1145/1250662.1250709  0.676
2007 Kim H, Joao JA, Mutlu O, Patt YN. Diverge-merge processor: Generalized and energy-efficient dynamic predication Ieee Micro. 27: 94-104. DOI: 10.1109/Mm.2007.9  0.695
2007 Emer J, Hill MD, Patt YN, Yi JJ, Chiou D, Sendag R. Single-threaded vs. multithreaded: Where should we focus? Ieee Micro. 27: 14-24. DOI: 10.1109/Mm.2007.109  0.408
2007 Qureshi MK, Suleman MA, Patt YN. Line distillation: Increasing cache capacity by filtering unused words in cache lines Proceedings - International Symposium On High-Performance Computer Architecture. 250-259. DOI: 10.1109/HPCA.2007.346202  0.626
2007 Srinath S, Mutlu O, Kim H, Patt YN. Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers Proceedings - International Symposium On High-Performance Computer Architecture. 63-74. DOI: 10.1109/HPCA.2007.346185  0.641
2007 Kim H, Joao JA, Mutlu O, Patt YN. Profile-assisted compiler support for dynamic predication in diverge-merge processors International Symposium On Code Generation and Optimization, Cgo 2007. 367-378. DOI: 10.1109/CGO.2007.31  0.589
2006 Mutlu O, Kim H, Patt YN. Address-value delta (AVD) prediction: A hardware technique for efficiently parallelizing dependent cache misses Ieee Transactions On Computers. 55: 1491-1507. DOI: 10.1109/Tc.2006.191  0.718
2006 Kim H, Mutlu O, Stark J, Patt YN. Wish branches: Enabling adaptive and aggressive predicated execution Ieee Micro. 26: 48-58. DOI: 10.1109/Mm.2006.27  0.688
2006 Mutlu O, Kim H, Patt YN. Efficient runahead execution: Power-efficient memory latency tolerance Ieee Micro. 26: 10-20. DOI: 10.1109/Mm.2006.10  0.702
2006 Qureshi MK, Patt YN. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches Proceedings of the Annual International Symposium On Microarchitecture, Micro. 423-432. DOI: 10.1109/MICRO.2006.49  0.718
2006 Kim H, Joao JA, Mutlu O, Patt YN. Diverge-merge processor (DMP): Dynamic predicated execution of complex control-flow graphs based on frequently executed paths Proceedings of the Annual International Symposium On Microarchitecture, Micro. 53-64. DOI: 10.1109/MICRO.2006.20  0.587
2006 Qureshi MK, Lynch DN, Mutlu O, Patt YN. A case for MLP-aware cache replacement Proceedings - International Symposium On Computer Architecture. 2006: 167-177. DOI: 10.1109/ISCA.2006.5  0.774
2006 Kim H, Suleman MA, Mutlu O, Patt YN. 2D-profiling: Detecting input-dependent branches with a single input data set Proceedings of the Cgo 2006 - the 4th International Symposium On Code Generation and Optimization. 159-172. DOI: 10.1109/CGO.2006.1  0.52
2005 Mutlu O, Kim H, Armstrong DN, Patt YN. An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors Ieee Transactions On Computers. 54: 1556-1571. DOI: 10.1109/Tc.2005.190  0.73
2005 Kim H, Mutlu O, Stark J, Patt YN. Wish branches: Combining conditional branching and predication for adaptive predicated execution Proceedings of the Annual International Symposium On Microarchitecture, Micro. 43-54. DOI: 10.1109/MICRO.2005.38  0.552
2005 Mutlu O, Kim H, Patt YN. Address-value delta (AVD) prediction: Increasing the effectiveness of runahead execution by exploiting regular memory allocation patterns Proceedings of the Annual International Symposium On Microarchitecture, Micro. 233-244. DOI: 10.1109/MICRO.2005.11  0.61
2005 Mutlu O, Kim H, Stark J, Patt YN. On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor Ieee Computer Architecture Letters. 4: 2-2. DOI: 10.1109/L-Ca.2005.1  0.701
2005 Qureshi MK, Thompson D, Patt YN. The V-Way cache: Demand-based associativity via global replacement Proceedings - International Symposium On Computer Architecture. 544-555. DOI: 10.1109/ISCA.2005.52  0.705
2005 Mutlu O, Kim H, Patt YN. Techniques for efficient processing in runahead execution engines Proceedings - International Symposium On Computer Architecture. 370-381. DOI: 10.1109/ISCA.2005.49  0.619
2005 Qureshi MK, Mutlu O, Patt YN. Microarchitecture-based introspection: A technique for transient-fault tolerance in microprocessors Proceedings of the International Conference On Dependable Systems and Networks. 434-443. DOI: 10.1109/DSN.2005.62  0.742
2005 Mutlu O, Kim H, Armstrong DN, Patt YN. Using the first-level caches as filters to reduce the pollution caused by speculative memory references International Journal of Parallel Programming. 33: 529-559. DOI: 10.1007/S10766-005-7304-X  0.727
2004 Mutlu O, Kim H, Armstrong DN, Patt YN. Understanding the effects of wrong-path memory references on processor performance Acm International Conference Proceeding Series. 68: 56-64. DOI: 10.1145/1054943.1054951  0.605
2004 Mutlu O, Kim H, Armstrong DN, Patt YN. Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance Proceedings - Symposium On Computer Architecture and High Performance Computing. 2-9.  0.616
2004 Armstrong DN, Kim H, Mutlu O, Patt YN. Wrong path events: Exploiting unusual and illegal program behavior for early misprediction detection and recovery Proceedings of the Annual International Symposium On Microarchitecture, Micro. 119-128.  0.426
2003 Mutlu O, Stark J, Wilkerson C, Patt YN. Runahead Execution: An Effective Alternative to Large Instruction Windows Ieee Micro. 23: 20-25. DOI: 10.1109/Mm.2003.1261383  0.625
2003 Mutlu O, Stark J, Wilkerson C, Patt YN. Runahead execution: An alternative to very large instruction windows for out-of-order processors Proceedings - International Symposium On High-Performance Computer Architecture. 12: 129-140. DOI: 10.1109/HPCA.2003.1183532  0.624
2003 Racunas P, Patt YN. Partitioned First-Level Cache Design for Clustered Microarchitectures Proceedings of the International Conference On Supercomputing. 22-31.  0.392
2002 Chappell RS, Tseng F, Yoaz A, Patt YN. Microarchitectural support for precomputation microthreads Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2002: 74-84. DOI: 10.1109/MICRO.2002.1176240  0.786
2002 Chappell RS, Tseng F, Yoaz A, Patt YN. Difficult-path branch prediction using subordinate microthreads Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 307-317.  0.788
2000 Ganger GR, McKusick MK, Soules CAN, Patt YN. Soft updates: A solution to the metadata update problem in file systems Acm Transactions On Computer Systems. 18: 127-153. DOI: 10.1145/350853.350863  0.447
1999 Patel SJ, Friendly DH, Patt YN. Evaluation of design options for the trace cache fetch mechanism Ieee Transactions On Computers. 48: 193-204. DOI: 10.1109/12.752661  0.392
1998 Ganger GR, Patt YN. Using system-level models to evaluate I/O subsystem designs Ieee Transactions On Computers. 47: 667-678. DOI: 10.1109/12.689646  0.331
1997 Patt YN. Identifying Obstacles In The Path To More Ieee Computer. 30: 32-32. DOI: 10.1109/Mc.1997.642795  0.304
1997 Patt YN, Patel SJ, Evers M, Friendly DH, Stark J. One billionTransistors, one uniprocessor, one chip Computer. 30: 51-57. DOI: 10.1109/2.612249  0.449
1997 Jourdan S, Stark J, Hsing TH, Patt YN. Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution International Journal of Parallel Programming. 25: 363-383. DOI: 10.1007/Bf02699883  0.377
1997 Chang PY, Evens M, Patt YN. Improving branch prediction accuracy by reducing pattern history table interference International Journal of Parallel Programming. 25: 339-362. DOI: 10.1007/Bf02699882  0.409
1996 Chang P, Hao E, Yeh T, Patt Y. Branch Classification: A New Mechanism for Improving Branch Predictor Performance International Journal of Parallel Programming. 24: 133-158. DOI: 10.1007/Bf03356745  0.413
1995 Melvin S, Patt Y. Enhancing instruction scheduling with a block-structured ISA International Journal of Parallel Programming. 23: 221-243. DOI: 10.1007/Bf02577867  0.444
1994 Ganger GR, Worthington BL, Hou RY, Patt YN. Disk Arrays High-Performance, High-Reliability Storage Subsystems Computer. 27: 30-36. DOI: 10.1109/2.268882  0.377
1994 Patt YN. The I/O Subsystem A Candidate for Improvement Computer. 27: 15-16. DOI: 10.1109/2.268880  0.319
1992 Uvieghara GA, Hwu WmW, Nakagome Y, Jeong DK, Hodges DA, Patt YN, Lee DD. An Experimental Single-Chip Data Flow CPU Ieee Journal of Solid-State Circuits. 27: 17-28. DOI: 10.1109/4.109554  0.475
1992 Siegel HJ, Abraham S, Bain WL, Batcher KE, Casavant TL, DeGroot D, Dennis JB, Douglas DC, Feng TY, Goodman JR, Huang A, Jordan HF, Robert Jump J, Patt YN, Smith AJ, et al. Report of the purdue workshop on grand challenges in computer architecture for the support of high performance computing Journal of Parallel and Distributed Computing. 16: 199-211. DOI: 10.1016/0743-7315(92)90033-J  0.402
1987 Hwu WMW, Patt YN. Checkpoint Repair for High-Performance Out-of-Order Execution Machines Ieee Transactions On Computers. 1496-1514. DOI: 10.1109/Tc.1987.5009500  0.456
1986 Despain AM, Patt YN, Dobry TP, Chang JH, Citrin W. HIGH PERFORMANCE PROLOG, THE MULTIPLICATIVE EFFECT OF SEVERAL LEVELS OF IMPLEMENTATION Proceedings - Ieee Computer Society International Conference. 178-184.  0.337
1985 Dobry TP, Despain AM, Patt YN. PERFORMANCE STUDIES OF A PROLOG MACHINE ARCHITECTURE Conference Proceedings - Annual Symposium On Computer Architecture. 180-190.  0.324
1983 Schaefer MT, Patt YN. Improving the performance of UCSD Pascal via microprogramming on the PDP-11/60 Acm Sigmicro Newsletter. 14: 140-148. DOI: 10.1145/1096419.1096440  0.358
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