| Year |
Citation |
Score |
| 2023 |
Diab S, Nassereldine A, Alser M, Gómez Luna J, Mutlu O, El Hajj I. A framework for high-throughput sequence alignment using real processing-in-memory systems. Bioinformatics (Oxford, England). 39. PMID 36971586 DOI: 10.1093/bioinformatics/btad155 |
0.318 |
|
| 2023 |
Lindegger J, Cali DS, Alser M, Gómez-Luna J, Ghiasi NM, Mutlu O. Scrooge: A Fast and Memory-Frugal Genomic Sequence Aligner for CPUs, GPUs, and ASICs. Bioinformatics (Oxford, England). PMID 36961334 DOI: 10.1093/bioinformatics/btad151 |
0.326 |
|
| 2021 |
Sadrosadati M, Mirhosseini A, Hajiabadi A, Ehsani SB, Falahati H, Sarbazi-Azad H, Drumond M, Falsafi B, Ausavarungnirun R, Mutlu O. Highly Concurrent Latency-tolerant Register Files for GPUs Acm Transactions On Computer Systems. 37: 1-36. DOI: 10.1145/3419973 |
0.379 |
|
| 2021 |
Jafri SMAH, Hassan H, Hemani A, Mutlu O. Refresh Triggered Computation Acm Transactions On Architecture and Code Optimization. 18: 1-29. DOI: 10.1145/3417708 |
0.353 |
|
| 2020 |
Mutlu O, Kim JS. RowHammer: A Retrospective Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1555-1571. DOI: 10.1109/Tcad.2019.2915318 |
0.43 |
|
| 2020 |
Alser M, Bingöl Z, Cali DS, Kim JS, Ghose S, Alkan C, Mutlu O. Accelerating Genome Analysis: A Primer on an Ongoing Journey Ieee Micro. 40: 65-75. DOI: 10.1109/Mm.2020.3013728 |
0.347 |
|
| 2020 |
Theocharides T, Shafique M, Choi J, Mutlu O. Guest Editorial: Robust Resource-Constrained Systems for Machine Learning Ieee Design & Test of Computers. 37: 5-7. DOI: 10.1109/Mdat.2020.2971201 |
0.367 |
|
| 2020 |
Rezaei SHS, Modarressi M, Ausavarungnirun R, Sadrosadati M, Mutlu O, Daneshtalab M. NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories Ieee Computer Architecture Letters. 19: 80-83. DOI: 10.1109/Lca.2020.2990599 |
0.456 |
|
| 2019 |
Alser M, Hassan H, Kumar A, Mutlu O, Alkan C. Shouji: A Fast and Efficient Pre-Alignment Filter for Sequence Alignment. Bioinformatics (Oxford, England). PMID 30923804 DOI: 10.1093/Bioinformatics/Btz234 |
0.389 |
|
| 2019 |
Ghose S, Boroumand A, Kim JS, Gómez-Luna J, Mutlu O. Processing-in-memory: A workload-driven perspective Journal of Reproduction and Development. 63. DOI: 10.1147/Jrd.2019.2934048 |
0.458 |
|
| 2019 |
Ghose S, Li T, Hajinazar N, Senol Cali D, Mutlu O. Demystifying ComplexWorkload-DRAM Interactions Acm Sigmetrics Performance Evaluation Review. 47: 93-93. DOI: 10.1145/3376930.3376989 |
0.307 |
|
| 2019 |
Ghose S, Li T, Hajinazar N, Cali DS, Mutlu O. Demystifying Complex Workload-DRAM Interactions Proceedings of the Acm On Measurement and Analysis of Computing Systems. 3: 1-50. DOI: 10.1145/3366708 |
0.33 |
|
| 2019 |
Sadrosadati M, Ehsani SB, Falahati H, Ausavarungnirun R, Tavakkol A, Abaee M, Orosa L, Wang Y, Sarbazi-Azad H, Mutlu O. ITAP: Idle-Time-Aware Power Management for GPU Execution Units Acm Transactions On Architecture and Code Optimization. 16: 3. DOI: 10.1145/3291606 |
0.737 |
|
| 2019 |
Orosa L, Azevedo R, Mutlu O. AVPP: Address-first Value-next Predictor with Value Prefetching for Improving the Efficiency of Load Value Prediction Acm Transactions On Architecture and Code Optimization. 15: 49. DOI: 10.1145/3239567 |
0.364 |
|
| 2019 |
Salkhordeh R, Mutlu O, Asadi H. An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories Ieee Transactions On Computers. 68: 1114-1130. DOI: 10.1109/Tc.2019.2906597 |
0.428 |
|
| 2019 |
Mutlu O, Ghose S, Gómez-Luna J, Ausavarungnirun R. Processing data where it makes sense: Enabling in-memory computation Microprocessors and Microsystems. 67: 28-41. DOI: 10.1016/J.Micpro.2019.01.009 |
0.46 |
|
| 2018 |
Kim JS, Senol Cali D, Xin H, Lee D, Ghose S, Alser M, Hassan H, Ergin O, Alkan C, Mutlu O. GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies. Bmc Genomics. 19: 89. PMID 29764378 DOI: 10.1186/s12864-018-4460-0 |
0.736 |
|
| 2018 |
Senol Cali D, Kim JS, Ghose S, Alkan C, Mutlu O. Nanopore sequencing technology and tools for genome assembly: computational analysis of the current state, bottlenecks and future directions. Briefings in Bioinformatics. PMID 29617724 DOI: 10.1093/Bib/Bby017 |
0.352 |
|
| 2018 |
Sadrosadati M, Mirhosseini A, Ehsani SB, Sarbazi-Azad H, Drumond M, Falsafi B, Ausavarungnirun R, Mutlu O. LTRF Acm Sigplan Notices. 53: 489-502. DOI: 10.1145/3296957.3173211 |
0.36 |
|
| 2018 |
Ausavarungnirun R, Miller V, Landgraf J, Ghose S, Gandhi J, Jog A, Rossbach CJ, Mutlu O. MASK Acm Sigplan Notices. 53: 503-518. DOI: 10.1145/3296957.3173169 |
0.406 |
|
| 2018 |
Ausavarungnirun R, Landgraf J, Miller V, Ghose S, Gandhi J, Rossbach CJ, Mutlu O. Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors Operating Systems Review. 52: 27-44. DOI: 10.1145/3273982.3273986 |
0.455 |
|
| 2018 |
Mutlu O, Mahlke S, Conte T, Hwu W. Iterative Modulo Scheduling Ieee Micro. 38: 115-117. DOI: 10.1109/Mm.2018.011441569 |
0.673 |
|
| 2017 |
Alser M, Hassan H, Xin H, Ergin O, Mutlu O, Alkan C. GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping. Bioinformatics (Oxford, England). PMID 28575161 DOI: 10.1093/Bioinformatics/Btx342 |
0.749 |
|
| 2017 |
Lu Y, Shu J, Sun L, Mutlu O. Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency Ieee Transactions On Parallel and Distributed Systems. 1-1. DOI: 10.1109/Tpds.2017.2701364 |
0.46 |
|
| 2017 |
Khan S, Wilkerson C, Lee D, Alameldeen AR, Mutlu O. A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM Ieee Computer Architecture Letters. 16: 88-93. DOI: 10.1109/Lca.2016.2624298 |
0.327 |
|
| 2017 |
Boroumand A, Ghose S, Patel M, Hassan H, Lucia B, Hsieh K, Malladi KT, Zheng H, Mutlu O. LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory Ieee Computer Architecture Letters. 16: 46-50. DOI: 10.1109/Lca.2016.2577557 |
0.444 |
|
| 2017 |
Fukami A, Ghose S, Luo Y, Cai Y, Mutlu O. Improving the reliability of chip-off forensic analysis of NAND flash memory devices Digital Investigation. 20. DOI: 10.1016/J.Diin.2017.01.011 |
0.418 |
|
| 2017 |
Seshadri V, Mutlu O. Simple Operations in Memory to Reduce Data Movement Advances in Computers. 106: 107-166. DOI: 10.1016/Bs.Adcom.2017.04.004 |
0.446 |
|
| 2016 |
Hsieh K, Ebrahimi E, Kim G, Chatterjee N, O'Connor M, Vijaykumar N, Mutlu O, Keckler SW. Transparent offloading and mapping (TOM) Acm Sigarch Computer Architecture News. 44: 204-216. DOI: 10.1145/3007787.3001159 |
0.368 |
|
| 2016 |
Pattnaik A, Tang X, Jog A, Kayiran O, Mishra AK, Kandemir MT, Mutlu O, Das CR. Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 11: 31-44. DOI: 10.1145/2967938.2967940 |
0.407 |
|
| 2016 |
Jog A, Kayiran O, Pattnaik A, Kandemir MT, Mutlu O, Iyer R, Das CR. Exploiting Core Criticality for Enhanced GPU Performance Acm Sigmetrics Performance Evaluation Review. 44: 351-363. DOI: 10.1145/2964791.2901468 |
0.347 |
|
| 2016 |
Jog A, Kayiran O, Pattnaik A, Kandemir MT, Mutlu O, Iyer R, Das CR. Exploiting core criticality for enhanced GPU performance Sigmetrics/ Performance 2016 - Proceedings of the Sigmetrics/Performance Joint International Conference On Measurement and Modeling of Computer Science. 351-363. DOI: 10.1145/2896377.2901468 |
0.347 |
|
| 2016 |
Yazdanbakhsh A, Pekhimenko G, Thwaites B, Esmaeilzadeh H, Mutlu O, Mowry TC. RFVP: Rollback-free value prediction with safe-To-Approximate loads Acm Transactions On Architecture and Code Optimization. 12. DOI: 10.1145/2836168 |
0.465 |
|
| 2016 |
Lee D, Ghose S, Pekhimenko G, Khan S, Mutlu O. Simultaneous multi-layer access: Improving 3d-stacked memory bandwidth at low cost Acm Transactions On Architecture and Code Optimization. 12. DOI: 10.1145/2832911 |
0.342 |
|
| 2016 |
Subramanian L, Lee D, Seshadri V, Rastogi H, Mutlu O. BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling Ieee Transactions On Parallel and Distributed Systems. 27: 3071-3087. DOI: 10.1109/Tpds.2016.2526003 |
0.477 |
|
| 2016 |
Ausavarungnirun R, Ghose S, Kayiran O, Loh GH, Das CR, Kandemir MT, Mutlu O. Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 2016: 25-38. DOI: 10.1109/PACT.2015.38 |
0.37 |
|
| 2016 |
Mutlu O, Belgard R, Tredennick N, Schlansker M. The 2014 MICRO Test of Time Award Winners: From 1978 to 1992 Ieee Micro. 36: 60. DOI: 10.1109/Mm.2016.7 |
0.33 |
|
| 2016 |
Mutlu O, Belgard R, Gross TR, Jouppi NR, Hennessy JL, Przybylski S, Rowen C, Patt YN, Hwu WW, Melvin SW, Shebanow MC, Yeh T, Wolfe A. Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor Ieee Micro. 36: 70-85. DOI: 10.1109/Mm.2016.66 |
0.779 |
|
| 2016 |
Yazdanbakhsh A, Thwaites B, Esmaeilzadeh H, Pekhimenko G, Mutlu O, Mowry TC. Mitigating the Memory Bottleneck with Approximate Load Value Prediction Ieee Design and Test. 33: 32-42. DOI: 10.1109/Mdat.2015.2504899 |
0.454 |
|
| 2016 |
Kim Y, Yang W, Mutlu O. Ramulator: A fast and extensible DRAM simulator Ieee Computer Architecture Letters. 15: 45-49. DOI: 10.1109/Lca.2015.2414456 |
0.308 |
|
| 2016 |
Luo Y, Ghose S, Cai Y, Haratsch EF, Mutlu O. Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory Ieee Journal On Selected Areas in Communications. 34: 2294-2311. DOI: 10.1109/Jsac.2016.2603608 |
0.343 |
|
| 2016 |
Hsieh K, Ebrahim E, Kim G, Chatterjee N, O'Connor M, Vijaykumar N, Mutlu O, Keckler SW. Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems Proceedings - 2016 43rd International Symposium On Computer Architecture, Isca 2016. 204-216. DOI: 10.1109/ISCA.2016.27 |
0.374 |
|
| 2016 |
Hassan H, Pekhimenko G, Vijaykumar N, Seshadri V, Lee D, Ergin O, Mutlu O. ChargeCache: Reducing DRAM latency by exploiting row access locality Proceedings - International Symposium On High-Performance Computer Architecture. 2016: 581-593. DOI: 10.1109/HPCA.2016.7446096 |
0.367 |
|
| 2016 |
Chang KK, Nair PJ, Lee D, Ghose S, Qureshi MK, Mutlu O. Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM Proceedings - International Symposium On High-Performance Computer Architecture. 2016: 568-580. DOI: 10.1109/HPCA.2016.7446095 |
0.681 |
|
| 2016 |
Kim H, de Niz D, Andersson B, Klein M, Mutlu O, Rajkumar R. Bounding and reducing memory interference in COTS-based multi-core systems Real-Time Systems. 1-40. DOI: 10.1007/S11241-016-9248-1 |
0.456 |
|
| 2015 |
Xin H, Greth J, Emmons J, Pekhimenko G, Kingsford C, Alkan C, Mutlu O. Shifted Hamming distance: a fast and accurate SIMD-friendly filter to accelerate alignment verification in read mapping. Bioinformatics (Oxford, England). 31: 1553-60. PMID 25577434 DOI: 10.1093/Bioinformatics/Btu856 |
0.334 |
|
| 2015 |
Lee D, Hormozdiari F, Xin H, Hach F, Mutlu O, Alkan C. Fast and accurate mapping of Complete Genomics reads. Methods (San Diego, Calif.). 79: 3-10. PMID 25461772 DOI: 10.1016/J.Ymeth.2014.10.012 |
0.319 |
|
| 2015 |
Usui H, Subramanian L, Chang KKW, Mutlu O. DASH: Deadline-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators Acm Transactions On Architecture and Code Optimization. 12. DOI: 10.1145/2847255 |
0.484 |
|
| 2015 |
Seshadri V, Mullins T, Boroumand A, Mutlu O, Gibbons PB, Kozuch MA, Mowry TC. Gather-scatter DRAM: In-DRAM address translation to improve the spatial locality of non-unit strided accesses Proceedings of the Annual International Symposium On Microarchitecture, Micro. 5: 267-280. DOI: 10.1145/2830772.2830820 |
0.313 |
|
| 2015 |
Wang H, Isci C, Subramanian L, Choi J, Qian D, Mutlu O. A-DRM Acm Sigplan Notices. 50: 93-106. DOI: 10.1145/2817817.2731202 |
0.307 |
|
| 2015 |
Meza J, Wu Q, Kumar S, Mutlu O. A Large-Scale Study of Flash Memory Failures in the Field Acm Sigmetrics Performance Evaluation Review. 43: 177-190. DOI: 10.1145/2796314.2745848 |
0.303 |
|
| 2015 |
Ahn J, Hong S, Yoo S, Mutlu O, Choi K. A scalable processing-in-memory accelerator for parallel graph processing Proceedings - International Symposium On Computer Architecture. 13: 105-117. DOI: 10.1145/2749469.2750386 |
0.325 |
|
| 2015 |
Ahn J, Yoo S, Mutlu O, Choi K. PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture Proceedings - International Symposium On Computer Architecture. 13: 336-348. DOI: 10.1145/2749469.2750385 |
0.385 |
|
| 2015 |
Seshadri V, Pekhimenko G, Ruwase O, Mutlu O, Gibbons PB, Kozuch MA, Mowry TC, Chilimbi T. Page overlays: An enhanced virtual memory framework to enable fine-grained memory management Proceedings - International Symposium On Computer Architecture. 13: 79-91. DOI: 10.1145/2749469.2750379 |
0.343 |
|
| 2015 |
Meza J, Wu Q, Kumar S, Mutlu O. A large-scale study of flash memory failures in the field Performance Evaluation Review. 43: 177-190. DOI: 10.1145/2745844.2745848 |
0.304 |
|
| 2015 |
Lu Y, Shu J, Guo J, Li S, Mutlu O. High-performance and lightweight transaction support in flash-based SSDs Ieee Transactions On Computers. 64: 2819-2832. DOI: 10.1109/Tc.2015.2389828 |
0.475 |
|
| 2015 |
Kayiran O, Nachiappan NC, Jog A, Ausavarungnirun R, Kandemir MT, Loh GH, Mutlu O, Das CR. Managing GPU Concurrency in Heterogeneous Architectures Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2015: 114-126. DOI: 10.1109/MICRO.2014.62 |
0.375 |
|
| 2015 |
Zhao J, Mutlu O, Xie Y. FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2015: 153-165. DOI: 10.1109/MICRO.2014.47 |
0.332 |
|
| 2015 |
Seshadri V, Hsieh K, Boroumand A, Lee D, Kozuch MA, Mutlu O, Gibbons PB, Mowry TC. Fast Bulk Bitwise and and or in DRAM Ieee Computer Architecture Letters. 14: 127-131. DOI: 10.1109/Lca.2015.2434872 |
0.363 |
|
| 2015 |
Pekhimenko G, Bolotin E, O'Connor M, Mutlu O, Mowry TC, Keckler SW. Toggle-Aware Compression for GPUs Ieee Computer Architecture Letters. 14: 164-168. DOI: 10.1109/Lca.2015.2430853 |
0.434 |
|
| 2015 |
Qureshi MK, Kim DH, Khan S, Nair PJ, Mutlu O. AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems Proceedings of the International Conference On Dependable Systems and Networks. 2015: 427-437. DOI: 10.1109/DSN.2015.58 |
0.659 |
|
| 2015 |
Mutlu O. Main memory scaling: Challenges and solution directions More Than Moore Technologies For Next Generation Computer Design. 127-153. DOI: 10.1007/978-1-4939-2163-8_6 |
0.312 |
|
| 2014 |
Seshadri V, Yedkar S, Xin H, Mutlu O, Gibbons PB, Kozuch MA, Mowry TC. Mitigating prefetcher-caused pollution using informed caching policies for prefetched blocks Acm Transactions On Architecture and Code Optimization. 11. DOI: 10.1145/2677956 |
0.435 |
|
| 2014 |
Yoon H, Meza J, Muralimanohar N, Jouppi NP, Mutlu O. Efficient data mapping and buffering techniques for multilevel cell phase-change memories Acm Transactions On Architecture and Code Optimization. 11. DOI: 10.1145/2669365 |
0.41 |
|
| 2014 |
Lu Y, Shu J, Sun L, Mutlu O. Loose-Ordering Consistency for persistent memory 2014 32nd Ieee International Conference On Computer Design, Iccd 2014. 216-223. DOI: 10.1109/ICCD.2014.6974684 |
0.36 |
|
| 2013 |
Xin H, Lee D, Hormozdiari F, Yedkar S, Mutlu O, Alkan C. Accelerating read mapping with FastHASH. Bmc Genomics. 14: S13. PMID 23369189 DOI: 10.1186/1471-2164-14-S1-S13 |
0.358 |
|
| 2013 |
Seshadri V, Kim Y, Fallin C, Lee D, Ausavarungnirun R, Pekhimenko G, Luo Y, Mutlu O, Gibbons PB, Kozuch MA, Mowry TC. RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization Micro 2013 - Proceedings of the 46th Annual Ieee/Acm International Symposium On Microarchitecture. 185-197. DOI: 10.1145/2540708.2540725 |
0.309 |
|
| 2013 |
Pekhimenko G, Seshadri V, Kim Y, Xin H, Mutlu O, Gibbons PB, Kozuch MA, Mowry TC. Linearly compressed pages: A low-complexity, low-latency main memory compression framework Micro 2013 - Proceedings of the 46th Annual Ieee/Acm International Symposium On Microarchitecture. 172-184. DOI: 10.1145/2540708.2540724 |
0.359 |
|
| 2013 |
Jog A, Kayiran O, Chidambaram Nachiappan N, Mishra AK, Kandemir MT, Mutlu O, Iyer R, Das CR. OWL Acm Sigarch Computer Architecture News. 41: 395-406. DOI: 10.1145/2490301.2451158 |
0.372 |
|
| 2013 |
Joao JA, Suleman MA, Mutlu O, Patt YN. Utility-based acceleration of multithreaded applications on asymmetric CMPs Proceedings - International Symposium On Computer Architecture. 154-165. DOI: 10.1145/2485922.2485936 |
0.638 |
|
| 2013 |
Kultursay E, Kandemir M, Sivasubramaniam A, Mutlu O. Evaluating STT-RAM as an energy-efficient main memory alternative Ispass 2013 - Ieee International Symposium On Performance Analysis of Systems and Software. 256-267. DOI: 10.1109/ISPASS.2013.6557176 |
0.325 |
|
| 2013 |
Mutlu O. Memory scaling: A systems architecture perspective 2013 5th Ieee International Memory Workshop, Imw 2013. 21-25. DOI: 10.1109/IMW.2013.6582088 |
0.322 |
|
| 2013 |
Lu Y, Shu J, Guo J, Li S, Mutlu O. LightTx: A lightweight transactional design in flash-based SSDs to support flexible transactions 2013 Ieee 31st International Conference On Computer Design, Iccd 2013. 115-122. DOI: 10.1109/ICCD.2013.6657033 |
0.321 |
|
| 2013 |
Subramanian L, Seshadri V, Kim Y, Jaiyen B, Mutlu O. MISE: Providing performance predictability and improving fairness in shared main memory systems Proceedings - International Symposium On High-Performance Computer Architecture. 639-650. DOI: 10.1109/HPCA.2013.6522356 |
0.314 |
|
| 2012 |
Nachiappan NC, Mishra AK, Kandemir M, Sivasubramaniam A, Mutlu O, Das CR. Application-aware prefetch prioritization in on-chip networks Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 441-442. DOI: 10.1145/2370816.2370886 |
0.338 |
|
| 2012 |
Seshadri V, Mutlu O, Kozuch MA, Mowry TC. The evicted-address filter: A unified mechanism to address both cache pollution and thrashing Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 355-366. DOI: 10.1145/2370816.2370868 |
0.372 |
|
| 2012 |
Liu J, Jaiyen B, Veras R, Mutlu O. RAIDR Acm Sigarch Computer Architecture News. 40: 1-12. DOI: 10.1145/2366231.2337161 |
0.34 |
|
| 2012 |
Joao JA, Suleman MA, Mutlu O, Patt YN. Bottleneck identification and scheduling in multithreaded applications Acm Sigarch Computer Architecture News. 40: 223-234. DOI: 10.1145/2189750.2151001 |
0.346 |
|
| 2012 |
Ebrahimi E, Lee CJ, Mutlu O, Patt YN. Fairness via source throttling: A configurable and high-performance fairness substrate for multicore memory systems Acm Transactions On Computer Systems. 30. DOI: 10.1145/2166879.2166881 |
0.69 |
|
| 2012 |
Joao JA, Suleman MA, Mutlu O, Patt YN. Bottleneck identification and scheduling in multithreaded applications International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 223-234. DOI: 10.1145/2150976.2151001 |
0.657 |
|
| 2012 |
Grot B, Hestness J, Keckler S, Mutlu O. A QoS-enabled on-die interconnect fabric for kilo-node chips Ieee Micro. 32: 17-25. DOI: 10.1109/Mm.2012.18 |
0.344 |
|
| 2012 |
Meza J, Chang J, Yoon H, Mutlu O, Ranganathan P. Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management Ieee Computer Architecture Letters. 11: 61-64. DOI: 10.1109/L-Ca.2012.2 |
0.463 |
|
| 2012 |
Kim Y, Seshadri V, Lee D, Liu J, Mutlu O. A case for exploiting subarray-level parallelism (SALP) in DRAM Proceedings - International Symposium On Computer Architecture. 368-379. DOI: 10.1109/ISCA.2012.6237032 |
0.362 |
|
| 2012 |
Liu J, Jaiyen B, Veras R, Mutlu O. RAIDR: Retention-aware intelligent DRAM refresh Proceedings - International Symposium On Computer Architecture. 1-12. DOI: 10.1109/ISCA.2012.6237001 |
0.345 |
|
| 2012 |
Meza J, Li J, Mutlu O. A case for small row buffers in non-volatile main memories Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 484-485. DOI: 10.1109/ICCD.2012.6378685 |
0.372 |
|
| 2012 |
Yoon H, Meza J, Ausavarungnirun R, Harding RA, Mutlu O. Row buffer locality aware caching policies for hybrid memories Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 337-344. DOI: 10.1109/ICCD.2012.6378661 |
0.329 |
|
| 2011 |
Ebrahimi E, Miftakhutdinov R, Fallin C, Lee CJ, Joao JA, Mutlu O, Patt YN. Parallel application memory scheduling Proceedings of the Annual International Symposium On Microarchitecture, Micro. 362-373. DOI: 10.1145/2155620.2155663 |
0.664 |
|
| 2011 |
Narasiman V, Shebanow M, Lee CJ, Miftakhutdinov R, Mutlu O, Patt YN. Improving GPU performance via large warps and two-level warp scheduling Proceedings of the Annual International Symposium On Microarchitecture, Micro. 308-317. DOI: 10.1145/2155620.2155656 |
0.663 |
|
| 2011 |
Mutlu O. Memory systems in the many-core era Acm Sigplan Notices. 46: 77-78. DOI: 10.1145/2076022.1993489 |
0.315 |
|
| 2011 |
Ebrahimi E, Lee CJ, Mutlu O, Patt YN. Prefetch-aware shared-resource management for multi-core systems Proceedings - International Symposium On Computer Architecture. 141-152. DOI: 10.1145/2000064.2000081 |
0.642 |
|
| 2011 |
David H, Fallin C, Gorbatov E, Hanebutte UR, Mutlu O. Memory power management via dynamic voltage/frequency scaling Proceedings of the 8th Acm International Conference On Autonomic Computing, Icac 2011 and Co-Located Workshops. 31-40. DOI: 10.1145/1998582.1998590 |
0.32 |
|
| 2011 |
Lee CJ, Mutlu O, Narasiman V, Patt YN. Prefetch-aware memory controllers Ieee Transactions On Computers. 60: 1406-1430. DOI: 10.1109/Tc.2010.214 |
0.689 |
|
| 2011 |
Patt YN, Mutlu O. Top picks [Guest editors' introduction] Ieee Micro. 31: 6-10. DOI: 10.1109/Mm.2011.16 |
0.608 |
|
| 2011 |
Kim Y, Papamichael M, Mutlu O, Harchol-Balter M. Thread cluster memory scheduling Ieee Micro. 31: 78-89. DOI: 10.1109/Mm.2011.15 |
0.43 |
|
| 2011 |
Das R, Mutlu O, Moscibroda T, Das C. Aérgia: A network-on-chip exploiting packet latency slack Ieee Micro. 31: 29-41. DOI: 10.1109/Mm.2010.98 |
0.337 |
|
| 2011 |
Suleman MA, Mutlu O, Joao J, Khubaib K, Patt YN. Data marshaling for multicore systems Ieee Micro. 31: 56-64. DOI: 10.1109/Mm.2010.105 |
0.636 |
|
| 2010 |
Ramirez T, Pajuelo A, Santana OJ, Mutlu O, Valero M. Efficient runahead threads Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 443-452. DOI: 10.1145/1854273.1854328 |
0.345 |
|
| 2010 |
Suleman MA, Mutlu O, Joao JA, Khubaib, Patt YN. Data marshaling for multi-core architectures Proceedings - International Symposium On Computer Architecture. 441-450. DOI: 10.1145/1815961.1816020 |
0.612 |
|
| 2010 |
Lee BC, Ipek E, Mutlu O, Burger D. Phase change memory architecture and the quest for scalability Communications of the Acm. 53: 99-106. DOI: 10.1145/1785414.1785441 |
0.42 |
|
| 2010 |
Ebrahimi E, Lee CJ, Mutlu O, Patt YN. Fairness via source throttling: A configurable and high-performance fairness substrate for multi-core memory systems International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 335-346. DOI: 10.1145/1736020.1736058 |
0.666 |
|
| 2010 |
Suleman MA, Mutlu O, Qureshi MK, Patt YN. Accelerating critical section execution with asymmetric multicore architectures Ieee Micro. 30: 60-70. DOI: 10.1109/Mm.2010.7 |
0.772 |
|
| 2010 |
Lee BC, Zhou P, Yang J, Zhang Y, Zhao B, Ipek E, Mutlu O, Burger D. Phase-Change Technology and the Future of Main Memory Ieee Micro. 30: 143-143. DOI: 10.1109/Mm.2010.24 |
0.396 |
|
| 2010 |
Kim Y, Han D, Mutlu O, Harchol-Balter M. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers Proceedings - International Symposium On High-Performance Computer Architecture. |
0.345 |
|
| 2009 |
Lee CJ, Narasiman V, Mutlu O, Patt YN. Improving memory bank-level parallelism in the presence of prefetching Proceedings of the Annual International Symposium On Microarchitecture, Micro. 327-336. DOI: 10.1145/1669112.1669155 |
0.659 |
|
| 2009 |
Ebrahimi E, Mutlu O, Lee CJ, Patt YN. Coordinated control of multiple prefetchers in multi-core systems Proceedings of the Annual International Symposium On Microarchitecture, Micro. 316-326. DOI: 10.1145/1669112.1669154 |
0.634 |
|
| 2009 |
Joao JA, Mutlu O, Patt YN. Flexible reference-counting-based hardware acceleration for garbage collection Proceedings - International Symposium On Computer Architecture. 418-428. DOI: 10.1145/1555754.1555806 |
0.664 |
|
| 2009 |
Constantinides K, Mutlu O, Austin T, Bertacco V. A flexible software-based framework for online detection of hardware defects Ieee Transactions On Computers. 58: 1063-1079. DOI: 10.1109/Tc.2009.52 |
0.4 |
|
| 2009 |
Kim H, Joao JA, Mutlu O, Lee CJ, Patt YN, Cohn R. Virtual program counter (VPC) prediction: Very low cost indirect branch prediction using conditional branch prediction hardware Ieee Transactions On Computers. 58: 1153-1170. DOI: 10.1109/Tc.2008.227 |
0.714 |
|
| 2009 |
Mutlu O, Moscibroda T. Parallelism-aware batch scheduling: Enabling high-performance and fair shared memory controllers Ieee Micro. 29: 22-32. DOI: 10.1109/Mm.2009.12 |
0.455 |
|
| 2009 |
Ebrahimi E, Mutlu O, Patt YN. Techniques for bandwidth-efficient prefetching of Linked Data Structures in hybrid prefetching systems Proceedings - International Symposium On High-Performance Computer Architecture. 7-17. DOI: 10.1109/HPCA.2009.4798232 |
0.692 |
|
| 2009 |
Suleman MA, Mutlu O, Qureshi MK, Patt YN. Accelerating Critical Section Execution with asymmetric multi-core architectures Acm Sigplan Notices. 44: 253-264. |
0.769 |
|
| 2008 |
Suleman MA, Mutlu O, Qureshi MK, Patt YN. Accelerating critical section execution asymmetricmulti-core architectures International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 253-264. DOI: 10.1145/1508244.1508274 |
0.768 |
|
| 2008 |
Joao JA, Mutlu O, Kim H, Agarwal R, Patt YN. Improving the performance of object-oriented languages with dynamic predication of indirect jumps Acm Sigops Operating Systems Review. 42: 80-90. DOI: 10.1145/1353535.1346293 |
0.319 |
|
| 2008 |
Joao JA, Mutlu O, Kim H, Agarwal R, Patt YN. Improving the performance of object-oriented languages with dynamic predication of indirect jumps Operating Systems Review (Acm). 42: 80-90. DOI: 10.1145/1346281.1346293 |
0.643 |
|
| 2008 |
Cho S, Li T, Mutlu O. Interaction of many-core computer architecture and operating systems Ieee Micro. 28: 2-5. DOI: 10.1109/Mm.2008.39 |
0.384 |
|
| 2008 |
Lee CJ, Mutlu O, Narasiman V, Patt YN. Prefetch-aware DRAM controllers Proceedings of the Annual International Symposium On Microarchitecture, Micro. 200-209. DOI: 10.1109/MICRO.2008.4771791 |
0.655 |
|
| 2008 |
Joao JA, Mutlu O, Kim H, Patt YN. Dynamic predication of indirect jumps Ieee Computer Architecture Letters. 7: 1-4. DOI: 10.1109/L-Ca.2007.7 |
0.723 |
|
| 2008 |
Mutlu O, Moscibroda T. Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared DRAM systems Proceedings - International Symposium On Computer Architecture. 63-74. DOI: 10.1109/ISCA.2008.7 |
0.349 |
|
| 2008 |
Chang JL, Kim H, Mutlu O, Patt YN. Performance-aware speculation control using wrong path usefulness prediction Proceedings - International Symposium On High-Performance Computer Architecture. 39-49. DOI: 10.1109/HPCA.2008.4658626 |
0.663 |
|
| 2007 |
Kim H, Joao JA, Mutlu O, Lee CJ, Patt YN, Cohn R. VPC prediction: Reducing the cost of indirect branches via hardware-based dynamic devirtualization Proceedings - International Symposium On Computer Architecture. 424-435. DOI: 10.1145/1250662.1250715 |
0.616 |
|
| 2007 |
Kim H, Joao JA, Mutlu O, Patt YN. Diverge-merge processor: Generalized and energy-efficient dynamic predication Ieee Micro. 27: 94-104. DOI: 10.1109/Mm.2007.9 |
0.719 |
|
| 2007 |
Mutlu O, Moscibroda T. Stall-time fair memory access scheduling for chip multiprocessors Proceedings of the Annual International Symposium On Microarchitecture, Micro. 146-158. DOI: 10.1109/MICRO.2007.21 |
0.317 |
|
| 2007 |
Srinath S, Mutlu O, Kim H, Patt YN. Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers Proceedings - International Symposium On High-Performance Computer Architecture. 63-74. DOI: 10.1109/HPCA.2007.346185 |
0.692 |
|
| 2007 |
Kim H, Joao JA, Mutlu O, Patt YN. Profile-assisted compiler support for dynamic predication in diverge-merge processors International Symposium On Code Generation and Optimization, Cgo 2007. 367-378. DOI: 10.1109/CGO.2007.31 |
0.637 |
|
| 2006 |
Mutlu O, Kim H, Patt YN. Address-value delta (AVD) prediction: A hardware technique for efficiently parallelizing dependent cache misses Ieee Transactions On Computers. 55: 1491-1507. DOI: 10.1109/Tc.2006.191 |
0.734 |
|
| 2006 |
Kim H, Mutlu O, Stark J, Patt YN. Wish branches: Enabling adaptive and aggressive predicated execution Ieee Micro. 26: 48-58. DOI: 10.1109/Mm.2006.27 |
0.699 |
|
| 2006 |
Mutlu O, Kim H, Patt YN. Efficient runahead execution: Power-efficient memory latency tolerance Ieee Micro. 26: 10-20. DOI: 10.1109/Mm.2006.10 |
0.736 |
|
| 2006 |
Kim H, Joao JA, Mutlu O, Patt YN. Diverge-merge processor (DMP): Dynamic predicated execution of complex control-flow graphs based on frequently executed paths Proceedings of the Annual International Symposium On Microarchitecture, Micro. 53-64. DOI: 10.1109/MICRO.2006.20 |
0.635 |
|
| 2006 |
Qureshi MK, Lynch DN, Mutlu O, Patt YN. A case for MLP-aware cache replacement Proceedings - International Symposium On Computer Architecture. 2006: 167-177. DOI: 10.1109/ISCA.2006.5 |
0.794 |
|
| 2006 |
Kim H, Suleman MA, Mutlu O, Patt YN. 2D-profiling: Detecting input-dependent branches with a single input data set Proceedings of the Cgo 2006 - the 4th International Symposium On Code Generation and Optimization. 159-172. DOI: 10.1109/CGO.2006.1 |
0.578 |
|
| 2005 |
Mutlu O, Kim H, Patt YN. Techniques for Efficient Processing in Runahead Execution Engines Acm Sigarch Computer Architecture News. 33: 370-381. DOI: 10.1145/1080695.1070000 |
0.358 |
|
| 2005 |
Mutlu O, Kim H, Armstrong DN, Patt YN. An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors Ieee Transactions On Computers. 54: 1556-1571. DOI: 10.1109/Tc.2005.190 |
0.763 |
|
| 2005 |
Kim H, Mutlu O, Stark J, Patt YN. Wish branches: Combining conditional branching and predication for adaptive predicated execution Proceedings of the Annual International Symposium On Microarchitecture, Micro. 43-54. DOI: 10.1109/MICRO.2005.38 |
0.61 |
|
| 2005 |
Mutlu O, Kim H, Patt YN. Address-value delta (AVD) prediction: Increasing the effectiveness of runahead execution by exploiting regular memory allocation patterns Proceedings of the Annual International Symposium On Microarchitecture, Micro. 233-244. DOI: 10.1109/MICRO.2005.11 |
0.659 |
|
| 2005 |
Mutlu O, Kim H, Stark J, Patt YN. On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor Ieee Computer Architecture Letters. 4: 2-2. DOI: 10.1109/L-Ca.2005.1 |
0.725 |
|
| 2005 |
Mutlu O, Kim H, Patt YN. Techniques for efficient processing in runahead execution engines Proceedings - International Symposium On Computer Architecture. 370-381. DOI: 10.1109/ISCA.2005.49 |
0.664 |
|
| 2005 |
Qureshi MK, Mutlu O, Patt YN. Microarchitecture-based introspection: A technique for transient-fault tolerance in microprocessors Proceedings of the International Conference On Dependable Systems and Networks. 434-443. DOI: 10.1109/DSN.2005.62 |
0.768 |
|
| 2005 |
Mutlu O, Kim H, Armstrong DN, Patt YN. Using the first-level caches as filters to reduce the pollution caused by speculative memory references International Journal of Parallel Programming. 33: 529-559. DOI: 10.1007/S10766-005-7304-X |
0.76 |
|
| 2004 |
Mutlu O, Kim H, Armstrong DN, Patt YN. Understanding the effects of wrong-path memory references on processor performance Acm International Conference Proceeding Series. 68: 56-64. DOI: 10.1145/1054943.1054951 |
0.674 |
|
| 2004 |
Mutlu O, Kim H, Armstrong DN, Patt YN. Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance Proceedings - Symposium On Computer Architecture and High Performance Computing. 2-9. |
0.681 |
|
| 2004 |
Armstrong DN, Kim H, Mutlu O, Patt YN. Wrong path events: Exploiting unusual and illegal program behavior for early misprediction detection and recovery Proceedings of the Annual International Symposium On Microarchitecture, Micro. 119-128. |
0.524 |
|
| 2003 |
Mutlu O, Stark J, Wilkerson C, Patt YN. Runahead Execution: An Effective Alternative to Large Instruction Windows Ieee Micro. 23: 20-25. DOI: 10.1109/Mm.2003.1261383 |
0.678 |
|
| 2003 |
Mutlu O, Stark J, Wilkerson C, Patt YN. Runahead execution: An alternative to very large instruction windows for out-of-order processors Proceedings - International Symposium On High-Performance Computer Architecture. 12: 129-140. DOI: 10.1109/HPCA.2003.1183532 |
0.674 |
|
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