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Yan Solihin - Publications

Affiliations: 
North Carolina State University, Raleigh, NC 
Area:
Electronics and Electrical Engineering, Computer Science
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60 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Alshboul M, Elnawawy H, Elkhouly R, Kimura K, Tuck J, Solihin Y. Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory Acm Transactions On Architecture and Code Optimization. 16: 18. DOI: 10.1145/3323091  0.79
2019 Solihin Y. Persistent Memory: Abstractions, Abstractions, and Abstractions Ieee Micro. 39: 65-66. DOI: 10.1109/Mm.2018.2885589  0.525
2016 Awad A, Balakrishnan G, Wang Y, Solihin Y. Accurate Cloning of the Memory Access Behavior Ipsj Transactions On System Lsi Design Methodology. 9: 49-60. DOI: 10.2197/Ipsjtsldm.9.49  0.664
2016 Awad A, Blagodurov S, Solihin Y. Write-aware management of NVM-based memory extensions Proceedings of the International Conference On Supercomputing. 1. DOI: 10.1145/2925426.2926284  0.468
2016 Awad A, Manadhata P, Haber S, Solihin Y, Horne W. Silent shredder: Zero-cost shredding for secure non-volatile main memory controllers International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 2: 263-276. DOI: 10.1145/2872362.2872377  0.481
2016 Wang Y, Balakrishnan G, Solihin Y. MeToo: Stochastic Modeling of Memory Traffic Timing Behavior Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 2016: 457-467. DOI: 10.1109/PACT.2015.36  0.48
2015 Balakrishnan G, Solihin Y. MEMST: Cloning memory behavior using stochastic traces Acm International Conference Proceeding Series. 5: 146-157. DOI: 10.1145/2818950.2818971  0.655
2015 Awad A, Kettering B, Solihin Y. Non-volatile memory host controller interface performance analysis in high-performance I/O systems Ispass 2015 - Ieee International Symposium On Performance Analysis of Systems and Software. 145-154. DOI: 10.1109/ISPASS.2015.7095793  0.398
2014 Tiwari D, Solihin Y. MapReuse: Reusing computation in an in-memory mapreduce system Proceedings of the International Parallel and Distributed Processing Symposium, Ipdps. 61-71. DOI: 10.1109/IPDPS.2014.18  0.324
2014 Awad A, Solihin Y. STM: Cloning the spatial and temporal memory access behavior Proceedings - International Symposium On High-Performance Computer Architecture. 237-247. DOI: 10.1109/HPCA.2014.6835935  0.43
2013 Samih A, Wang R, Krishna A, Maciocco C, Tai C, Solihin Y. Energy-efficient interconnect via Router Parking Proceedings - International Symposium On High-Performance Computer Architecture. 508-519. DOI: 10.1109/HPCA.2013.6522345  0.762
2013 Samih A, Jiang X, Han L, Solihin Y. Flexible capacity partitioning in many-core tiled CMPs Proceedings - 13th Ieee/Acm International Symposium On Cluster, Cloud, and Grid Computing, Ccgrid 2013. 490-497. DOI: 10.1109/CCGrid.2013.16  0.76
2012 Krishna A, Samih A, Solihin Y. Data sharing in multi-threaded applications and its impact on chip design Ispass 2012 - Ieee International Symposium On Performance Analysis of Systems and Software. 125-134. DOI: 10.1109/ISPASS.2012.6189219  0.771
2012 Tiwari D, Solihin Y. Modeling and analyzing key performance factors of shared memory MapReduce Proceedings of the 2012 Ieee 26th International Parallel and Distributed Processing Symposium, Ipdps 2012. 1306-1317. DOI: 10.1109/IPDPS.2012.119  0.333
2012 Balakrishnan G, Solihin Y. WEST: Cloning data cache behavior using stochastic traces Proceedings - International Symposium On High-Performance Computer Architecture. 387-398. DOI: 10.1109/HPCA.2012.6169042  0.605
2011 Samih A, Wang R, Maciocco C, Tai TYC, Solihin Y. A collaborative memory system for high-performance and cost-effective clustered architectures Acm International Conference Proceeding Series. 4-12. DOI: 10.1145/2377978.2377979  0.811
2011 Samih A, Solihin Y, Krishna A. Evaluating placement policies for managing capacity sharing in CMP architectures with private caches Transactions On Architecture and Code Optimization. 8. DOI: 10.1145/2019608.2019614  0.781
2011 Liu F, Solihin Y. Studying the impact of hardware prefetching and bandwidth partitioning in Chip-MultiProcessors Performance Evaluation Review. 39: 37-48. DOI: 10.1145/2007116.2007121  0.449
2011 Chhabray S, Solihin Y. I-NVMM: A secure non-volatile main memory system with incremental encryption Proceedings - International Symposium On Computer Architecture. 177-188. DOI: 10.1145/2000064.2000086  0.493
2011 Chhabra S, Rogers B, Solihin Y, Prvulovic M. SecureME: A hardware-software approach to full system security Proceedings of the International Conference On Supercomputing. 108-119. DOI: 10.1145/1995896.1995914  0.698
2011 Jiang X, Madan N, Zhao L, Upton M, Iyer R, Makineni S, Newell D, Solihin Y, Balasubramonian R. CHOP: Integrating DRAM caches for CMP server platforms Ieee Micro. 31: 99-108. DOI: 10.1109/Mm.2010.100  0.681
2011 Jiang X, Solihin Y. Architectural framework for supporting operating system survivability Proceedings - International Symposium On High-Performance Computer Architecture. 456-465. DOI: 10.1109/HPCA.2011.5749751  0.49
2011 Lee S, Tiwari D, Solihin Y, Tuck J. HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor Proceedings - International Symposium On High-Performance Computer Architecture. 99-110. DOI: 10.1109/HPCA.2011.5749720  0.314
2010 Liu F, Solihin Y. Understanding the behavior and implications of context switch misses Transactions On Architecture and Code Optimization. 7. DOI: 10.1145/1880043.1880048  0.385
2010 Guo F, Solihin Y, Zhao L, Iyer R. Quality of Service shared cache management in chip multiprocessor architecture Transactions On Architecture and Code Optimization. 7. DOI: 10.1145/1880037.1880039  0.443
2010 Tiwari D, Lee S, Tuck J, Solihin Y. MMT: Exploiting fine-grained parallelism in dynamic memory management Proceedings of the 2010 Ieee International Symposium On Parallel and Distributed Processing, Ipdps 2010. DOI: 10.1109/IPDPS.2010.5470428  0.45
2010 Chhabra S, Solihin Y. Green secure processors: Towards power-efficient secure processor design Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 6340: 329-351. DOI: 10.1007/978-3-642-17499-5_13  0.579
2010 Chhabra S, Solihin Y, Lal R, Hoekstra M. An analysis of secure processor architectures Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5890: 101-121. DOI: 10.1007/978-3-642-11389-5_6  0.382
2010 Liu F, Jiang X, Solihin Y. Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance Proceedings - International Symposium On High-Performance Computer Architecture.  0.411
2009 Tiwari D, Lee S, Tuck J, Solihin Y. Memory management thread for heap allocation intensive sequential applications Acm International Conference Proceeding Series. 35-42. DOI: 10.1145/1621960.1621967  0.449
2009 Rogers B, Krishna A, Bell G, Vu K, Jiang X, Solihin Y. Scaling the bandwidth wall: Challenges in and avenues for CMP scaling Proceedings - International Symposium On Computer Architecture. 371-382. DOI: 10.1145/1555754.1555801  0.569
2009 Venkataramani G, Doudalis I, Solihin Y, Prvulovic M. MemTracker: An accelerator for memory debugging and monitoring Transactions On Architecture and Code Optimization. 6. DOI: 10.1145/1543753.1543754  0.736
2009 Chhabra S, Rogers B, Solihin Y, Prvulovic M. Making secure processors OS- and performance-friendly Transactions On Architecture and Code Optimization. 5. DOI: 10.1145/1498690.1498691  0.797
2009 Lee J, Jung C, Lim D, Solihin Y. Prefetching with helper threads for loosely coupled multiprocessor systems Ieee Transactions On Parallel and Distributed Systems. 20: 1309-1324. DOI: 10.1109/Tpds.2008.224  0.583
2009 Jiang X, Solihin Y, Zhao L, Iyer R. Architecture support for improving bulk memory copying and initialization performance Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 169-180. DOI: 10.1109/PACT.2009.31  0.637
2008 Kharbutli M, Solihin Y. Counter-based cache replacement and bypassing algorithms Ieee Transactions On Computers. 57: 433-447. DOI: 10.1109/Tc.2007.70816  0.756
2008 Venkataramani G, Doudalis I, Solihin Y, Prvulovic M. FlexiTaint: A programmable accelerator for dynamic taint propagation Proceedings - International Symposium On High-Performance Computer Architecture. 173-184. DOI: 10.1109/HPCA.2008.4658637  0.722
2008 Rogers B, Yan C, Chhabra S, Prvulovic M, Solihin Y. Single-level integrity and confidentiality protection for distributed shared memory multiprocessors Proceedings - International Symposium On High-Performance Computer Architecture. 161-172. DOI: 10.1109/HPCA.2008.4658636  0.714
2007 Gambhir M, Gehringer EF, Solihin Y. Animations of important concepts in parallel computer architecture Proceedings of the 2007 Workshop On Computer Architecture Education, Wcae'07. 23-29. DOI: 10.1145/1275633.1275638  0.403
2007 Iyer R, Zhao L, Guo F, Illikkal R, Makineni S, Newell D, Solihin Y, Hsu L, Reinhardt S. QoS policies and architecture for cache/memory in CMP platforms Performance Evaluation Review. 35: 25-36. DOI: 10.1145/1269899.1254886  0.428
2007 Guo F, Kannan H, Zhao L, Illikkal R, Iyer R, Newell D, Solihin Y, Kozyrakis C. From chaos to QoS Acm Sigarch Computer Architecture News. 35: 21-30. DOI: 10.1145/1241601.1241608  0.451
2007 Guo F, Solihin Y, Zhao L, Iyer R. A framework for providing quality of service in chip multi-processors Proceedings of the Annual International Symposium On Microarchitecture, Micro. 343-355. DOI: 10.1109/MICRO.2007.17  0.313
2007 Rogers B, Chhabra S, Solihin Y, Prvulovic M. Using address independent seed encryption and bonsai merkle trees to make secure processors OS-and performance-friendly Proceedings of the Annual International Symposium On Microarchitecture, Micro. 183-194. DOI: 10.1109/MICRO.2007.16  0.741
2007 Venkataramani G, Roemer B, Solihin Y, Prvulovic M. MemTracker: Efficient and programmable support for memory access monitoring and debugging Proceedings - International Symposium On High-Performance Computer Architecture. 273-284. DOI: 10.1109/HPCA.2007.346205  0.724
2006 Shetty R, Kharbutli M, Solihin Y, Prvulovic M. HeapMon: A helper-thread approach to programmable, automatic and low-overhead memory bug detection Ibm Journal of Research and Development. 50: 261-275. DOI: 10.1147/Rd.502.0261  0.798
2006 Kharbutli M, Jiang X, Solihin Y, Venkataramani G, Prvulovic M. Comprehensively and efficiently protecting the heap International Conference On Architectural Support For Programming Languages and Operating Systems - Asplos. 207-218. DOI: 10.1145/1168857.1168884  0.745
2006 Rogers B, Prvulovic M, Solihin Y. Efficient data protection for distributed shared memory multiprocessors Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 2006: 84-94. DOI: 10.1145/1152154.1152170  0.713
2006 Yan C, Rogers B, Englender D, Solihin Y, Prvulovic M. Improving cost, performance, and security of memory encryption and authentication Proceedings - International Symposium On Computer Architecture. 2006: 179-190. DOI: 10.1109/ISCA.2006.22  0.71
2006 Jung C, Lim D, Lee J, Solihin Y. Helper thread prefetching for loosely-coupled multiprocessor systems 20th International Parallel and Distributed Processing Symposium, Ipdps 2006. 2006. DOI: 10.1109/IPDPS.2006.1639375  0.512
2005 Rogers B, Solihin Y, Prvulovic M. Memory predecryption: hiding the latency overhead of memory encryption Acm Sigarch Computer Architecture News. 33: 27-33. DOI: 10.1145/1055626.1055631  0.761
2005 Kharbutli M, Solihin Y, Lee J. Eliminating conflict misses using prime number-based cache indexing Ieee Transactions On Computers. 54: 573-586. DOI: 10.1109/Tc.2005.79  0.792
2005 Solihin Y, Guo F, Kim S. Predicting cache space contention in utility computing servers Proceedings - 19th Ieee International Parallel and Distributed Processing Symposium, Ipdps 2005. 2005. DOI: 10.1109/IPDPS.2005.354  0.386
2005 Chandra D, Guo F, Kim S, Solihin Y. Predicting inter-thread cache contention on a chip multi-processor architecture Proceedings - International Symposium On High-Performance Computer Architecture. 340-351. DOI: 10.1109/HPCA.2005.27  0.354
2004 Kim S, Chandra D, Solihin Y. Fair cache sharing and partitioning in a chip multiprocessor architecture Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 111-122.  0.362
2004 Kharbutli M, Irwin K, Solihin Y, Lee J. Using prime numbers for cache indexing to eliminate conflict misses Ieee High-Performance Computer Architecture Symposium Proceedings. 10: 288-299.  0.392
2003 Solihin Y, Lee J, Torrellas J. Correlation prefetching with a user-level memory thread Ieee Transactions On Parallel and Distributed Systems. 14: 563-580. DOI: 10.1109/Tpds.2003.1206504  0.738
2002 Solihin Y, Lee J, Torrellas J. Using a user-level memory thread for correlation prefetching Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 171-182.  0.713
2001 Solihin Y, Lee J, Torrellas J. Automatic code mapping on an intelligent memory architecture Ieee Transactions On Computers. 50: 1248-1266. DOI: 10.1109/12.966498  0.706
2001 Solihin Y, Lee J, Torrellas J. Adaptively mapping code in an intelligent memory architecture Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2107: 71-84.  0.672
1999 Solihin Y, Leedham CG. Integral ratio: A new class of global thresholding techniques for handwriting images Ieee Transactions On Pattern Analysis and Machine Intelligence. 21: 761-768. DOI: 10.1109/34.784289  0.306
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