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Volkan Kursun, Ph.D. - Publications

Affiliations: 
2004 Electrical and Computer Engineering University of Rochester, Rochester, NY 
 2004-2008 Electrical and Computer Engineering University of Wisconsin, Madison, Madison, WI 
 2008- Electronic and Computer Engineering Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong 
Area:
Electronics and Electrical Engineering
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149 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Sun Y, He W, Mao Z, Jiao H, Kursun V. Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density Ieee Transactions On Circuits and Systems. 67: 2431-2441. DOI: 10.1109/Tcsi.2020.2980074  0.685
2019 Gundu AK, Kursun V. Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input–Output Repeaters Ieee Transactions On Very Large Scale Integration Systems. 27: 1537-1547. DOI: 10.1109/Tvlsi.2019.2902215  0.624
2018 Sun Y, He W, Mao Z, Jiao H, Kursun V. Metallic-CN-Removal-Tolerant High-Yield Six-CN-MOSFET SRAM Cell for Carbon-Based Embedded Memory Ieee Transactions On Electron Devices. 65: 1230-1238. DOI: 10.1109/Ted.2018.2798667  0.69
2017 Sun Y, He W, Mao Z, Jiao H, Kursun V. High-Yield and Robust 9T SRAM Cell Tolerant to Removal of Metallic Carbon Nanotubes Ieee Transactions On Device and Materials Reliability. 17: 20-31. DOI: 10.1109/Tdmr.2017.2668761  0.664
2017 Sun Y, He W, Mao Z, Kursun V. Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic Microelectronics Journal. 62: 12-20. DOI: 10.1016/J.Mejo.2017.01.010  0.676
2016 Salahuddin SM, Kursun V. Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability Journal of Circuits, Systems and Computers. 25. DOI: 10.1142/S0218126616400090  0.523
2016 Salahuddin SM, Kursun V. Asymmetrical FinFET SRAM cells with wider read noise margin and lower leakage currents Ieee Region 10 Annual International Conference, Proceedings/Tencon. 2016. DOI: 10.1109/TENCON.2015.7373000  0.553
2016 Jiao H, Qiu Y, Kursun V. Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode Integration, the Vlsi Journal. 53: 68-79. DOI: 10.1016/J.Vlsi.2015.12.003  0.678
2016 Jiao H, Qiu Y, Kursun V. Low power and robust memory circuits with asymmetrical ground gating Microelectronics Journal. 48: 109-119. DOI: 10.1016/J.Mejo.2015.11.009  0.749
2015 Salahuddin SM, Kursun V, Jiao H. Finfet sram cells with asymmetrical bitline access transistors for enhanced read stability Transactions On Electrical and Electronic Materials. 16: 293-302. DOI: 10.4313/Teem.2015.16.6.293  0.723
2015 Salahuddin SM, Kursun V. High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage margins Proceedings of the 14th International Symposium On Integrated Circuits, Isic 2014. 312-315. DOI: 10.1109/ISICIR.2014.7029512  0.493
2015 Zhu H, Kursun V. 2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 2932-2935. DOI: 10.1109/ISCAS.2015.7169301  0.473
2015 Sun Y, Kursun V. Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 2720-2723. DOI: 10.1109/ISCAS.2015.7169248  0.533
2014 Sun Y, Jiao H, Kursun V. A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2014.2350674  0.707
2014 Zhu H, Kursun V. Novel low-leakage and high-speed triple-threshold-voltage buffers with skewed inputs and outputs Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 2013-2021. DOI: 10.1109/Tcsi.2014.2304661  0.657
2014 Zhu H, Kursun V. A comprehensive comparison of data stability enhancement techniques with novel nanoscale SRAM cells under parameter fluctuations Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 1473-1484. DOI: 10.1109/Tcsi.2013.2289411  0.64
2014 Sun Y, Kursun V. Carbon nanotubes blowing new life into NP dynamic CMOS circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 420-428. DOI: 10.1109/Tcsi.2013.2268131  0.572
2014 Zhu H, Kursun V. A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells Proceedings - Ieee International Symposium On Circuits and Systems. 2185-2188. DOI: 10.1109/ISCAS.2014.6865602  0.571
2014 Zhu H, Kursun V. Triple-threshold-voltage 9-transistor SRAM cell for data stability and energy-efficiency at ultra-low power supply voltages Proceedings of the International Conference On Microelectronics, Icm. 2015: 176-179. DOI: 10.1109/ICM.2014.7071835  0.526
2014 Sun Y, Jiao H, Kursun V. Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins Proceedings of the International Conference On Microelectronics, Icm. 2015: 164-167. DOI: 10.1109/ICM.2014.7071832  0.395
2014 Jiao H, Kursun V. Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits Microelectronics Journal. 45: 1125-1131. DOI: 10.1016/J.Mejo.2014.05.006  0.699
2013 Jiao H, Kursun V. Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc. 150-155. DOI: 10.1109/VLSI-SoC.2013.6673267  0.69
2013 Jiao H, Kursun V. Reactivation noise suppression with sleep signal slew rate modulation in MTCMOS circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 533-545. DOI: 10.1109/Tvlsi.2012.2190116  0.67
2013 Sarfraz K, Kursun V. Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 64-69. DOI: 10.1109/ISVLSI.2013.6654624  0.492
2013 Jiao H, Kursun V. Ground gated 8T SRAM cells with enhanced read and hold data stability Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 52-57. DOI: 10.1109/ISVLSI.2013.6654622  0.672
2013 Zhu H, Kursun V. Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells Proceedings - International Symposium On Quality Electronic Design, Isqed. 448-453. DOI: 10.1109/ISQED.2013.6523650  0.52
2013 Salahuddin S, Jiao H, Kursun V. A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability Proceedings - International Symposium On Quality Electronic Design, Isqed. 353-358. DOI: 10.1109/ISQED.2013.6523634  0.458
2013 Jiao H, Kursun V. Novel high electrical quality seven-transistor memory cell with asymmetrical ground gating Isocc 2013 - 2013 International Soc Design Conference. 255-258. DOI: 10.1109/ISOCC.2013.6864021  0.634
2013 Sun Y, Kursun V. A comparison of high-frequency 32-bit dynamic adders with conventional silicon and novel carbon nanotube transistor technologies Isocc 2013 - 2013 International Soc Design Conference. 39-42. DOI: 10.1109/ISOCC.2013.6863980  0.315
2013 Zhu H, Kursun V. Novel dual-threshold-voltage energy-efficient buffers for driving large extrinsic load capacitance Proceedings - Ieee International Symposium On Circuits and Systems. 3000-3003. DOI: 10.1109/ISCAS.2013.6572510  0.445
2013 Salahuddin SM, Jiao H, Kursun V. Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability Proceedings - Ieee International Symposium On Circuits and Systems. 2331-2334. DOI: 10.1109/ISCAS.2013.6572345  0.46
2013 Sun Y, Kursun V. Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors Proceedings - Ieee International Symposium On Circuits and Systems. 2119-2122. DOI: 10.1109/ISCAS.2013.6572292  0.411
2013 Salahuddin SM, Kursun V. Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 25-28. DOI: 10.1109/ICECS.2013.6815336  0.53
2013 Salahuddin SM, Jiao H, Kursun V. Characterization of FinFET SRAM cells with asymmetrically gate underlapped bitline access transistors under process parameter fluctuations 2013 Ieee International Conference of Electron Devices and Solid-State Circuits, Edssc 2013. DOI: 10.1109/EDSSC.2013.6628163  0.422
2012 Jiao H, Kursun V. Threshold voltage tuning for faster activation with lower noise in tri-mode MTCMOS circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 741-745. DOI: 10.1109/Tvlsi.2011.2110663  0.741
2012 Sun Y, Kursun V. NP dynamic CMOS resurrection with carbon nanotube field effect transistors Isocc 2012 - 2012 International Soc Design Conference. 13-16. DOI: 10.1109/ISOCC.2012.6406913  0.356
2012 Jiao H, Kursun V. Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits Isocc 2012 - 2012 International Soc Design Conference. 466-469. DOI: 10.1109/ISOCC.2012.6406897  0.605
2012 Jiao H, Kursun V. Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 484-487. DOI: 10.1109/ISCAS.2012.6272070  0.698
2012 Jiao H, Kursun V. Low power and robust ground gated memory banks with combined write assist techniques 2012 Ieee Faible Tension Faible Consommation, Ftfc 2012. DOI: 10.1109/FTFC.2012.6231727  0.701
2012 Zhu H, Kursun V. Novel triple-threshold-voltage eight-transistor SRAM circuit with enhanced overall electrical quality 2012 Ieee Faible Tension Faible Consommation, Ftfc 2012. DOI: 10.1109/FTFC.2012.6231725  0.48
2011 Sun Y, Kursun V. N-Type carbon-nanotube MOSFET device profile optimization for very large scale integration Transactions On Electrical and Electronic Materials. 12: 43-50. DOI: 10.4313/Teem.2011.12.2.43  0.562
2011 Jiao H, Kursun V. Noise-aware data preserving sequential MTCMOS circuits with dynamic forward body bias Journal of Circuits, Systems and Computers. 20: 125-145. DOI: 10.1142/S0218126611007116  0.749
2011 Jiao H, Kursun V. Asymmetrical ground gating for low leakage and data robust sleep mode in memory banks Proceedings of 2011 International Symposium On Vlsi Design, Automation and Test, Vlsi-Dat 2011. 205-208. DOI: 10.1109/VDAT.2011.5783611  0.715
2011 Jiao H, Kursun V. Ground bouncing noise suppression techniques for data preserving sequential MTCMOS circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 763-773. DOI: 10.1109/Tvlsi.2009.2039761  0.702
2011 Tawfik SA, Kursun V. Multi-threshold voltage FinFET sequential circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 151-156. DOI: 10.1109/Tvlsi.2009.2028028  0.81
2011 Jiao H, Kursun V. Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits International System On Chip Conference. 365-370. DOI: 10.1109/SOCC.2011.6085093  0.667
2011 Sun Y, Kursun V. Substrate bias considerations for low leakage 16nm p-channel carbon nanotube transistors Midwest Symposium On Circuits and Systems. DOI: 10.1109/MWSCAS.2011.6026407  0.321
2011 Sun Y, Kursun V. Leakage current and bottom gate voltage considerations in developing maximum performance 16nm N-channel carbon nanotube transistors Proceedings - Ieee International Symposium On Circuits and Systems. 2513-2516. DOI: 10.1109/ISCAS.2011.5938115  0.397
2011 Zhu H, Kursun V. Application-specific selection of 6T SRAM cells offering superior performance and quality with a triple-threshold-voltage CMOS technology Proceedings of the 3rd Asia Symposium On Quality Electronic Design, Asqed 2011. 68-73. DOI: 10.1109/ASQED.2011.6111704  0.436
2011 Zhu H, Kursun V. Symmetrical triple-threshold-voltage nine-transistor SRAM circuit with superior noise immunity and overall electrical quality 2011 International Soc Design Conference, Isocc 2011. 333-336.  0.474
2010 Jiao H, Kursun V. Low-leakage and compact registers with easy-sleep mode Journal of Low Power Electronics. 6: 263-279. DOI: 10.1166/Jolpe.2010.1080  0.695
2010 Jiao H, Kursun V. Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits Proceedings of the 2010 18th Ieee/Ifip International Conference On Vlsi and System-On-Chip, Vlsi-Soc 2010. 347-351. DOI: 10.1109/VLSISOC.2010.5642685  0.711
2010 Tawfik SA, Kursun V. Dual supply voltages and dual clock frequencies for lower clock power and suppressed temperature-gradient-induced clock skew Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 347-355. DOI: 10.1109/Tvlsi.2008.2010549  0.737
2010 Jiao H, Kursun V. Ground-bouncing-noise-aware combinational MTCMOS circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 2053-2065. DOI: 10.1109/Tcsi.2010.2041505  0.687
2010 Jiao H, Kursun V. Power gated SRAM circuits with data retention capability and high immunity to noise: A comparison for reliability in low leakage sleep mode 2010 International Soc Design Conference, Isocc 2010. 5-8. DOI: 10.1109/SOCDC.2010.5682988  0.739
2010 Jiao H, Kursun V. How forward body bias helps to reduce ground bouncing noise and silicon area in MTCMOS circuits: Divulging the basic mechanism 2010 International Soc Design Conference, Isocc 2010. 9-12. DOI: 10.1109/SOCDC.2010.5682985  0.659
2010 Zhu H, Kursun V. Data stability enhancement techniques for nanoscale memory circuits: 7T memory design tradeoffs and options in 80nm UMC CMOS technology 2010 International Soc Design Conference, Isocc 2010. 158-161. DOI: 10.1109/SOCDC.2010.5682947  0.497
2010 Jiao H, Kursun V. Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 3845-3848. DOI: 10.1109/ISCAS.2010.5537716  0.649
2010 Sun Y, Kursun V. Physical parametric analysis of 16nm N-channel Carbon-Nanotube transistors for manufacturability Proceedings of the International Conference On Microelectronics, Icm. 28-31. DOI: 10.1109/ICM.2010.5696141  0.327
2010 Jiao H, Kursun V. High-speed and low-leakage MTCMOS memory registers Proceedings of the 2nd Asia Symposium On Quality Electronic Design, Asqed 2010. 17-22. DOI: 10.1109/ASQED.2010.5548162  0.665
2010 Jiao H, Kursun V. Dynamic forward body bias enhanced tri-mode MTCMOS Proceedings of the 2nd Asia Symposium On Quality Electronic Design, Asqed 2010. 33-37. DOI: 10.1109/ASQED.2010.5548161  0.679
2009 Tawfik SA, Kursun V. Robust FinFET memory circuits with P-type data access transistors for higher integration density and reduced leakage power Journal of Low Power Electronics. 5: 497-508. DOI: 10.1166/Jolpe.2009.1048  0.799
2009 Tawfik SA, Kursun V. Low power and high speed multi threshold voltage interface circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 638-645. DOI: 10.1109/Tvlsi.2008.2006793  0.798
2009 Jiao H, Kursun V. Sleep transistor forward body bias: An extra knob to lower ground bouncing noise in MTCMOS circuits 2009 International Soc Design Conference, Isocc 2009. 216-219. DOI: 10.1109/SOCDC.2009.5423813  0.638
2009 Tawfik SA, Kursun V. FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations Midwest Symposium On Circuits and Systems. 431-434. DOI: 10.1109/MWSCAS.2009.5236062  0.674
2009 Tawfik SA, Kursun V. Manufacturable low-power latches for standard tied-double-gate FinFET technologies Midwest Symposium On Circuits and Systems. 471-474. DOI: 10.1109/MWSCAS.2009.5236052  0.747
2009 Tawfik SA, Kursun V. Mutual exploration of FinFET technology and circuit design options for implementing compact brute-force latches 2009 1st Asia Symposium On Quality Electronic Design, Asqed 2009. 1-8. DOI: 10.1109/ASQED.2009.5206309  0.755
2009 Jiao H, Kursun V. Ground bouncing noise suppression techniques for MTCMOS circuits 2009 1st Asia Symposium On Quality Electronic Design, Asqed 2009. 64-70. DOI: 10.1109/ASQED.2009.5206297  0.662
2009 Tawfik SA, Kursun V. Parameter space exploration for robust and high-performance n-channel and p-channel symmetric double-gate FinFETs 2009 1st Asia Symposium On Quality Electronic Design, Asqed 2009. 246-251. DOI: 10.1109/ASQED.2009.5206260  0.631
2009 Kumar R, Kursun V. Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays Microelectronics Journal. 40: 1013-1025. DOI: 10.1016/J.Mejo.2009.02.006  0.631
2009 Tawfik SA, Kursun V. FinFET domino logic with independent gate keepers Microelectronics Journal. 40: 1531-1540. DOI: 10.1016/J.Mejo.2009.01.011  0.808
2009 Jiao H, Kursun V. Ground bouncing noise aware sequential MTCMOS circuits with data retention capability Isic-2009 - 12th International Symposium On Integrated Circuits, Proceedings. 534-537.  0.686
2009 Tawfik SA, Kursun V. Low-power and robust six-finFET memory cell using selective gate-drain/source overlap engineering Isic-2009 - 12th International Symposium On Integrated Circuits, Proceedings. 244-247.  0.764
2008 Tawfik SA, Kursun V. Clock distribution networks with gradual signal transition time relaxation for reduced power consumption Journal of Circuits, Systems and Computers. 17: 1173-1191. DOI: 10.1142/S0218126608004824  0.688
2008 Kumar R, Kursun V. Temperature-adaptive energy reduction techniques for nano-cmos circuits displaying reversed temperature dependence Journal of Circuits, Systems and Computers. 17: 423-438. DOI: 10.1142/S0218126608004393  0.623
2008 Kumar R, Liu Z, Kursun V. Technique for accurate power and energy measurement with the computer-aided design tools Journal of Circuits, Systems and Computers. 17: 399-421. DOI: 10.1142/S0218126608004381  0.645
2008 Liu Z, Kursun V. Characterization of a novel nine-transistor SRAM cell Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 488-492. DOI: 10.1109/Tvlsi.2007.915499  0.695
2008 Tawfik SA, Kursun V. Low-power and compact sequential circuits with independent-gate FinFETs Ieee Transactions On Electron Devices. 55: 60-70. DOI: 10.1109/Ted.2007.911039  0.797
2008 Tawfik SA, Kursun V. Stability enhancement techniques for SRAM circuits: A comparison 2008 International Soc Design Conference, Isocc 2008. 1. DOI: 10.1109/SOCDC.2008.4815586  0.745
2008 Tawfik SA, Kursun V. Portfolio of FinFET memories: Innovative techniques for an emerging technology 2008 International Soc Design Conference, Isocc 2008. 1. DOI: 10.1109/SOCDC.2008.4815583  0.742
2008 Kumar R, Kursun V. Temperature-adaptive dynamic voltage scaling for high temperature energy efficiency in subthreshold memory banks Midwest Symposium On Circuits and Systems. 562-565. DOI: 10.1109/MWSCAS.2008.4616861  0.452
2008 Liu Z, Kursun V. Characterization of wake-up delay versus sleep mode power consumption and sleep/active mode transition energy overhead tradeoffs in MTCMOS circuits Midwest Symposium On Circuits and Systems. 362-365. DOI: 10.1109/MWSCAS.2008.4616811  0.423
2008 Tawfik SA, Kursun V. Compact FinFET memory circuits with p-type data access transistors for low leakage and robust operation Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 855-860. DOI: 10.1109/ISQED.2008.4479850  0.785
2008 Tawfik SA, Kursun V. Characterization of new static independent-gate-biased FinFET latches and flip-flops under process variations Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 311-316. DOI: 10.1109/ISQED.2008.4479746  0.784
2008 Liu Z, Tawfik SA, Kursun V. Statistical data stability and leakage evaluation of FinFET SRAM cells with dynamic threshold voltage tuning under process parameter fluctuations Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 305-310. DOI: 10.1109/ISQED.2008.4479745  0.767
2008 Tawfik SA, Kursun V. Dynamic wordline voltage swing for low leakage and stable static memory banks Proceedings - Ieee International Symposium On Circuits and Systems. 1894-1897. DOI: 10.1109/ISCAS.2008.4541812  0.796
2008 Tawfik SA, Kursun V. Low power and robust 7T dual-Vt SRAM circuit Proceedings - Ieee International Symposium On Circuits and Systems. 1452-1455. DOI: 10.1109/ISCAS.2008.4541702  0.772
2008 Tawfik SA, Kursun V. Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits Proceedings - Ieee International Symposium On Circuits and Systems. 788-791. DOI: 10.1109/ISCAS.2008.4541536  0.759
2008 Tawfik SA, Kursun V. Asymmetric dual-gate multi-Fin keeper bias options and optimization for low power and robust FinFET domino logic Ieee Asia-Pacific Conference On Circuits and Systems, Proceedings, Apccas. 1720-1723. DOI: 10.1109/APCCAS.2008.4746371  0.803
2008 Tawfik SA, Kursun V. Multi-Vth finFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption Ieee Asia-Pacific Conference On Circuits and Systems, Proceedings, Apccas. 348-351. DOI: 10.1109/APCCAS.2008.4746031  0.794
2008 Kumar R, Kursun V. Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits Microelectronics Journal. 39: 1714-1727. DOI: 10.1016/J.Mejo.2008.02.003  0.634
2007 Tawfik SA, Kursun V. Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution Proceedings of the International Symposium On Low Power Electronics and Design. 62-67. DOI: 10.1145/1283780.1283795  0.713
2007 Liu Z, Kursun V. PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1311-1319. DOI: 10.1109/Tvlsi.2007.903947  0.719
2007 Tawfik SA, Kursun V. Low-power high-performance FinFET sequential circuits Proceedings - 20th Anniversary Ieee International Soc Conference. 145-148. DOI: 10.1109/SOCC.2007.4545446  0.777
2007 Liu Z, Tawfik SA, Kursun V. An independent-gate FinFET SRAM cell for high data stability and enhanced integration density Proceedings - 20th Anniversary Ieee International Soc Conference. 63-66. DOI: 10.1109/SOCC.2007.4545427  0.761
2007 Kumar R, Kursun V. Supply and threshold voltage optimization for temperature variation insensitive circuit performance: A comparison 2006 Ieee International Systems-On-Chip Conference, Soc. 89-90. DOI: 10.1109/SOCC.2006.283852  0.39
2007 Liu Z, Kursun V. Low energy MTCMOS with sleep transistor charge recycling Midwest Symposium On Circuits and Systems. 891-894. DOI: 10.1109/MWSCAS.2007.4488714  0.405
2007 Kumar R, Liu Z, Kursun V. Fundamental concepts of power and energy measurement with the computer-aided-design tools Midwest Symposium On Circuits and Systems. 863-866. DOI: 10.1109/MWSCAS.2007.4488709  0.47
2007 Kumar R, Kursun V. Temperature-adaptive body-bias and supply voltage scaling for enhanced energy efficiency in nano-CMOS circuits Midwest Symposium On Circuits and Systems. 702-705. DOI: 10.1109/MWSCAS.2007.4488675  0.46
2007 Tawfik SA, Kursun V. Dual-VDD clock distribution for low power and minimum temperature fluctuations induced skew Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 73-78. DOI: 10.1109/ISQED.2007.65  0.714
2007 Tawfik SA, Kursun V. High speed FinFET domino logic circuits with independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise Proceedings of the International Conference On Microelectronics, Icm. 175-178. DOI: 10.1109/ICM.2007.4497687  0.792
2007 Tawfik SA, Liu Z, Kursun V. Independent-gate and tied-gate FinFET SRAM circuits: Design guidelines for reduced area and enhanced stability Proceedings of the International Conference On Microelectronics, Icm. 171-174. DOI: 10.1109/ICM.2007.4497686  0.762
2007 Kumar R, Kursun V. Temperature-adaptive energy reduction for ultra-low power-supply-voltage subthreshold logic circuits Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 1280-1283. DOI: 10.1109/ICECS.2007.4511231  0.494
2007 Liu Z, Kursun V. New MTCMOS flip-flops with simple control circuitry and low leakage data retention capability Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 1276-1279. DOI: 10.1109/ICECS.2007.4511230  0.354
2007 Tawfik SA, Kursun V. Buffer insertion and sizing in clock distribution networks with gradual transition time relaxation for reduced power consumption Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 845-848. DOI: 10.1109/ICECS.2007.4511123  0.642
2007 Tawfik SA, Kursun V. Low power and stable FinFET SRAM with static independent gate bias for enhanced integration density Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 443-446. DOI: 10.1109/ICECS.2007.4511025  0.762
2007 Kumar R, Kursun V. Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits Microelectronics Journal. 38: 583-594. DOI: 10.1016/J.Mejo.2007.03.011  0.687
2007 Liu Z, Kursun V. High read stability and low leakage cache memory cell Proceedings - Ieee International Symposium On Circuits and Systems. 2774-2777.  0.452
2007 Liu Z, Kursun V. Charge recycling MTCMOS for low energy active/sleep mode transitions Proceedings - Ieee International Symposium On Circuits and Systems. 1389-1392.  0.422
2007 Tawfik SA, Kursun V. Low-power low-voltage hot-spot tolerant clocking with suppressed skew Proceedings - Ieee International Symposium On Circuits and Systems. 645-648.  0.722
2007 Tawfik SA, Kursun V. Multi-Vth level conversion circuits for multi-VDD systems Proceedings - Ieee International Symposium On Circuits and Systems. 1397-1400.  0.777
2007 Kursun V, Tawfik SA, Liu Z. Leakage-aware design of nanometer SoC Proceedings - Ieee International Symposium On Circuits and Systems. 3231-3234.  0.776
2006 Kumar R, Kursun V. Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits Ieee Transactions On Circuits and Systems Ii: Express Briefs. 53: 1078-1082. DOI: 10.1109/Tcsii.2006.882218  0.69
2006 Liu Z, Kursun V. Leakage biased pMOS sleep switch dynamic circuits Ieee Transactions On Circuits and Systems Ii: Express Briefs. 53: 1093-1097. DOI: 10.1109/Tcsii.2006.882206  0.712
2006 Liu Z, Kursun V. Leakage power characteristics of dynamic circuits in nanometer CMOS technologies Ieee Transactions On Circuits and Systems Ii: Express Briefs. 53: 692-696. DOI: 10.1109/Tcsii.2006.876463  0.744
2006 Kumar R, Kursun V. Temperature variation insensitive energy efficient CMOS circuits in a 65nm CMOS technology Midwest Symposium On Circuits and Systems. 2: 226-230. DOI: 10.1109/MWSCAS.2006.382251  0.486
2006 Liu Z, Kursun V. High speed low swing dynamic circuits with multiple supply and threshold voltages Proceedings - Ieee Computer Society Annual Symposium On Emerging Vlsi Technologies and Architectures 2006. 2006: 59-64. DOI: 10.1109/ISVLSI.2006.50  0.607
2006 Liu Z, Kursun V. Leakage biased sleep switch domino logic Proceedings - International Symposium On Quality Electronic Design, Isqed. 318-323. DOI: 10.1109/ISQED.2006.80  0.531
2006 Liu Z, Kursun V. Robust dynamic node low voltage swing domino logic with multiple threshold voltages Proceedings - International Symposium On Quality Electronic Design, Isqed. 31-36. DOI: 10.1109/ISQED.2006.112  0.597
2006 Liu Z, Kursun V. Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current Microelectronics Journal. 37: 812-820. DOI: 10.1016/J.Mejo.2006.01.001  0.718
2006 Kursun V, Friedman EG. Multi-Voltage CMOS Circuit Design Multi-Voltage Cmos Circuit Design. 1-225. DOI: 10.1002/0470033371  0.679
2006 Kumar R, Kursun V. Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies Proceedings - Ieee International Symposium On Circuits and Systems. 3858-3861.  0.509
2006 Kursun V, Liu Z. Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies Proceedings - Ieee International Symposium On Circuits and Systems. 3854-3857.  0.564
2006 Liu Z, Kursun V. Leakage current starved domino logic Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 428-433.  0.567
2006 Kumar R, Kursun V. A design methodology for temperature variation insensitive low power circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 410-415.  0.52
2005 Liu Z, Kursun V. Temperature dependent leakage power characteristics of dynamic circuits in sub-65 nm CMOS technologies Midwest Symposium On Circuits and Systems. 2005: 551-554. DOI: 10.1109/MWSCAS.2005.1594160  0.579
2005 Kumar R, Kursun V. Voltage optimization for temperature variation insensitive CMOS circuits Midwest Symposium On Circuits and Systems. 2005: 476-479. DOI: 10.1109/MWSCAS.2005.1594141  0.534
2005 Liu Z, Kursun V. Bidirectional dynamic node low voltage swing domino logic Midwest Symposium On Circuits and Systems. 2005: 295-298. DOI: 10.1109/MWSCAS.2005.1594097  0.577
2005 Kursun V, Schrom G, De VK, Friedman EG, Narendra SG. Cascode buffer for monolithic voltage conversion operating at high input supply voltages Proceedings - Ieee International Symposium On Circuits and Systems. 464-467. DOI: 10.1109/ISCAS.2005.1464625  0.663
2005 Kursun V, De VK, Friedman EG, Narendra SG. Monolithic voltage conversion in low-voltage CMOS technologies Microelectronics Journal. 36: 863-867. DOI: 10.1016/j.mejo.2005.03.008  0.66
2005 Kursun V, Narendra SG, De VK, Friedman EG. Cascode monolithic DC-DC converter for reliable operation at high input voltages Analog Integrated Circuits and Signal Processing. 42: 231-238. DOI: 10.1007/S10470-005-6757-6  0.68
2005 Liu Z, Kursun V. Shifted leakage power characteristics of dynamic circuits due to gate oxide tunneling Proceedings - Ieee International Soc Conference. 151-154.  0.55
2004 Kursun V, Friedman EG. Sleep switch dual threshold voltage domino logic with reduced standby leakage current Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 485-496. DOI: 10.1109/Tvlsi.2004.826198  0.72
2004 Kursun V, Narendra SG, De VK, Friedman EG. Low-voltage-swing monolithic dc-dc conversion Ieee Transactions On Circuits and Systems Ii: Express Briefs. 51: 241-248. DOI: 10.1109/Tcsii.2004.827557  0.69
2004 Schrom G, Hazucha P, Hahn JH, Kursun V, Gardner D, Narendra S, Karnik T, De V. Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation Proceedings of the International Symposium On Low Power Electronics and Design. 2004: 263-268. DOI: 10.1109/LPE.2004.241035  0.403
2004 Kursun V, Narendra SG, De VK, Friedman EG. High input voltage step-down DC-DC converters for integration in a low voltage CMOS process Proceedings - 5th International Symposium On Quality Electronic Design, Isqued 2004. 517-521. DOI: 10.1109/ISQED.2004.1283725  0.647
2004 Kursun V, Friedman EG. Node voltage dependent subthreshold leakage current characteristics of dynamic circuits Proceedings - 5th International Symposium On Quality Electronic Design, Isqued 2004. 104-109. DOI: 10.1109/ISQED.2004.1283658  0.679
2004 Kursun V, Friedman EG. Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.696
2004 Kursun V, Friedman EG. Forward body biased keeper for enhanced noise immunity in domino logic circuits Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.626
2004 Schrom G, Hazucha P, Hahn JH, Kursun V, Gardner D, Narendra S, Karnik T, De V. Feasibility of monolithic and 30-stacked DC-DC converters for microprocessors in 90nm technology generation Proceedings of the 2004 International Symposium On Lower Power Electronics and Design, Islped'04. 263-268.  0.395
2003 Kursun V, Friedman EG. Domino logic with variable threshold voltage keeper Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1080-1093. DOI: 10.1109/Tvlsi.2003.817515  0.74
2003 Kursun V, Narendra SG, De VK, Friedman EG. Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 514-522. DOI: 10.1109/Tvlsi.2003.812289  0.663
2003 Albonesi DH, Balasubramonian R, Dropsho SG, Dwarkadas S, Friedman EG, Huang MC, Kursun V, Magklis G, Scott ML, Semeraro G, Bose P, Buyuktosunoglu A, Cook PW, Schuster SE. Dynamically Tuning Processor Resources with Adaptive Processing Computer. 36: 49-50+4. DOI: 10.1109/Mc.2003.1250883  0.509
2003 Kursun V, Narendra SG, De VK, Friedman EG. Monolithic DC-DC converter analysis and MOSFET gate voltage optimization Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 279-284. DOI: 10.1109/ISQED.2003.1194746  0.608
2002 Dropsho S, Kursun V, Albonesi DH, Dwarkadas S, Friedman EG. Managing static leakage energy in microprocessor functional units Proceedings of the Annual International Symposium On Microarchitecture, Micro. 2002: 321-332. DOI: 10.1109/MICRO.2002.1176260  0.528
2002 Kursun V, Friedman EG. Variable threshold voltage keeper for contention reduction in dynamic circuits Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 314-318. DOI: 10.1109/ASIC.2002.1158077  0.717
2002 Kursun V, Friedman EG. Domino logic with dynamic body biased keeper European Solid-State Circuits Conference. 675-678.  0.698
2002 Kursun V, Secareanu RM, Friedman EG. CMOS voltage interface circuit for low power systems Proceedings - Ieee International Symposium On Circuits and Systems. 3.  0.83
2002 Kursun V, Narendra SG, De VK, Friedman EG. Efficiency analysis of a high frequency buck converter for on-chip integration with a dual-VDDmicroprocessor European Solid-State Circuits Conference. 743-746.  0.611
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