Year |
Citation |
Score |
2018 |
Alsafrjalani MH, Gordon-Ross A. Scheduling and Tuning for Low Energy in Heterogeneous and Configurable Multicore Systems The First Computers. 7: 25. DOI: 10.3390/Computers7020025 |
0.447 |
|
2018 |
Alsafrjalani MH, Gordon-Ross A. Low Effort Design Space Exploration Methodology for Configurable Caches The First Computers. 7: 21. DOI: 10.3390/Computers7020021 |
0.387 |
|
2018 |
Adegbija T, Gordon-Ross A. PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking Ieee Transactions On Very Large Scale Integration Systems. 26: 110-121. DOI: 10.1109/Tvlsi.2017.2757477 |
0.406 |
|
2018 |
Adegbija T, Rogacs A, Patel C, Gordon-Ross A. Microprocessor Optimizations for the Internet of Things: A Survey Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 7-20. DOI: 10.1109/Tcad.2017.2717782 |
0.407 |
|
2017 |
Adegbija T, Gordon-Ross A. TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems The First Computers. 7: 3. DOI: 10.3390/Computers7010003 |
0.403 |
|
2017 |
Wulf N, George AD, Gordon-Ross A. Optimizing FPGA Performance, Power, and Dependability with Linear Programming Acm Transactions On Reconfigurable Technology and Systems. 10: 1-23. DOI: 10.1145/3079756 |
0.407 |
|
2017 |
Abdel-Hafeez S, Gordon-Ross A. An Efficient O( $N$ ) Comparison-Free Sorting Algorithm Ieee Transactions On Very Large Scale Integration Systems. 25: 1930-1942. DOI: 10.1109/Tvlsi.2017.2661746 |
0.308 |
|
2016 |
Wulf N, George AD, Gordon-Ross A. A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing Acm Transactions On Reconfigurable Technology and Systems. 10: 1-29. DOI: 10.1145/2888400 |
0.391 |
|
2016 |
Kumar R, Gordon-Ross A. MACS: A Highly Customizable Low-Latency Communication Architecture Ieee Transactions On Parallel and Distributed Systems. 27: 237-249. DOI: 10.1109/Tpds.2015.2390631 |
0.374 |
|
2016 |
Zang W, Gordon-Ross A. CaPPS: cache partitioning with partial sharing for multi-core embedded systems Design Automation For Embedded Systems. 20: 65-92. DOI: 10.1007/S10617-015-9168-7 |
0.383 |
|
2015 |
Munir A, Antoon J, Gordon-Ross A. Modeling and Analysis of Fault Detection and Fault Tolerance in Wireless Sensor Networks Acm Transactions in Embedded Computing Systems. 14: 3. DOI: 10.1145/2680538 |
0.434 |
|
2015 |
Ding L, Lizarraga A, Shenoy A, Gordon-Ross A, Lysecky S, Lysecky R. Application-Specific Customization of Dynamic Profiling Mechanisms for Sensor Networks Ieee Access. 3: 303-322. DOI: 10.1109/Access.2015.2422783 |
0.759 |
|
2014 |
Munir A, Gordon-Ross A, Ranka S. Multi-Core Embedded Wireless Sensor Networks: Architecture and Applications Ieee Transactions On Parallel and Distributed Systems. 25: 1553-1562. DOI: 10.1109/Tpds.2013.219 |
0.586 |
|
2014 |
Munir A, Gordon-Ross A, Ranka S, Koushanfar F. A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems Journal of Parallel and Distributed Computing. 74: 1872-1890. DOI: 10.1016/J.Jpdc.2013.07.003 |
0.42 |
|
2014 |
Adegbija T, Gordon-Ross A, Munir A. Phase distance mapping: a phase-based cache tuning methodology for embedded systems Design Automation For Embedded Systems. 18: 251-278. DOI: 10.1007/S10617-014-9127-8 |
0.39 |
|
2013 |
Lizarraga A, Lysecky R, Lysecky S, Gordon-Ross A. Dynamic profiling and fuzzy-logic-based optimization of sensor network platforms Acm Transactions in Embedded Computing Systems. 13: 51. DOI: 10.1145/2539036.2539047 |
0.761 |
|
2013 |
Zang W, Gordon-Ross A. A survey on cache tuning from a power/energy perspective Acm Computing Surveys. 45. DOI: 10.1145/2480741.2480749 |
0.349 |
|
2013 |
Rawlins M, Gordon-Ross A. Adaptive loop caching using lightweight runtime control flow analysis Acm Transactions in Embedded Computing Systems. 12: 55. DOI: 10.1145/2435227.2435251 |
0.363 |
|
2013 |
Abdel-Hafeez S, Gordon-Ross A, Parhami B. Scalable digital CMOS comparator using a parallel prefix tree Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1989-1998. DOI: 10.1109/Tvlsi.2012.2222453 |
0.372 |
|
2013 |
Rawlins M, Gordon-Ross A. A Cache Tuning Heuristic for Multicore Architectures Ieee Transactions On Computers. 62: 1570-1583. DOI: 10.1109/Tc.2013.44 |
0.416 |
|
2013 |
Zang W, Gordon-Ross A. T-SPaCS-A two-level single-pass cache simulation methodology Ieee Transactions On Computers. 62: 390-403. DOI: 10.1109/Tc.2011.194 |
0.318 |
|
2013 |
Munir A, Gordon-Ross A, Lysecky S, Lysecky RL. A lightweight dynamic optimization methodology and application metrics estimation model for wireless sensor networks Sustainable Computing: Informatics and Systems. 3: 94-108. DOI: 10.1016/J.Suscom.2013.01.003 |
0.752 |
|
2013 |
Munir A, Koushanfar F, Gordon-Ross A, Ranka S. High-performance optimizations on tiled many-core embedded systems: A matrix multiplication case study Journal of Supercomputing. 66: 431-487. DOI: 10.1007/S11227-013-0916-9 |
0.446 |
|
2012 |
Jacobs A, Cieslewski G, George AD, Gordon-Ross A, Lam H. Reconfigurable fault tolerance: A comprehensive framework for reliable and adaptive FPGA-based space computing Acm Transactions On Reconfigurable Technology and Systems. 5. DOI: 10.1145/2392616.2392619 |
0.368 |
|
2012 |
Gordon-Ross A, Vahid F, Dutt N. Combining code reordering and cache configuration Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2362336.2399177 |
0.59 |
|
2012 |
Wang W, Mishra P, Gordon-Ross A. Dynamic Cache Reconfiguration for Soft Real-Time Systems Acm Transactions in Embedded Computing Systems. 11: 28. DOI: 10.1145/2220336.2220340 |
0.425 |
|
2012 |
Munir A, Ranka S, Gordon-Ross A. High-Performance Energy-Efficient Multicore Embedded Computing Ieee Transactions On Parallel and Distributed Systems. 23: 684-700. DOI: 10.1109/Tpds.2011.214 |
0.402 |
|
2012 |
Munir A, Gordon-Ross A. An MDP-Based Dynamic Optimization Methodology for Wireless Sensor Networks Ieee Transactions On Parallel and Distributed Systems. 23: 616-625. DOI: 10.1109/Tpds.2011.208 |
0.581 |
|
2012 |
Lizarraga A, Ding L, Hiner J, Lysecky R, Lysecky S, Gordon-Ross A. ATLeS-SN Design Automation For Embedded Systems. 16: 265-291. DOI: 10.1007/S10617-013-9109-2 |
0.75 |
|
2011 |
Abdel-Hafeez S, Gordon-Ross A. A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead Structure Circuits Systems and Signal Processing. 30: 1549-1572. DOI: 10.1007/S00034-011-9279-8 |
0.304 |
|
2010 |
Munir A, Gordon-Ross A. SIP-Based IMS Signaling Analysis for WiMax-3G Interworking Architectures Ieee Transactions On Mobile Computing. 9: 733-750. DOI: 10.1109/Tmc.2010.16 |
0.399 |
|
2010 |
Shenoy A, Hiner J, Lysecky S, Lysecky R, Gordon-Ross A. Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks Ieee Embedded Systems Letters. 2: 10-13. DOI: 10.1109/Les.2010.2045634 |
0.759 |
|
2009 |
Gordon-Ross A, Vahid F, Dutt ND. Fast configurable-cache tuning with a unified second-level cache Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 80-91. DOI: 10.1109/Tvlsi.2008.2002459 |
0.584 |
|
2005 |
Gordon-Ross A, Vahid F. Frequent loop detection using efficient nonintrusive on-chip hardware Ieee Transactions On Computers. 54: 1203-1215. DOI: 10.1109/Tc.2005.165 |
0.628 |
|
2003 |
Gordon-Ross A, Cotterell S, Vahid F. Tiny instruction caches for low power embedded systems Acm Transactions On Embedded Computing Systems (Tecs). 2: 449-481. DOI: 10.1145/950162.950163 |
0.62 |
|
2002 |
Gordon-Ross A, Cotterell S, Vahid F. Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example Ieee Computer Architecture Letters. 1: 2-2. DOI: 10.1109/L-Ca.2002.4 |
0.566 |
|
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