Rajeev R. Rao, Ph.D. - Publications
Affiliations: | 2006 | University of Michigan, Ann Arbor, Ann Arbor, MI |
Area:
Electronics and Electrical EngineeringYear | Citation | Score | |||
---|---|---|---|---|---|
2009 | Rao RR, Joshi V, Blaauw D, Sylvester D. Circuit optimization techniques to mitigate the effects of soft errors in combinational logic Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1640457.1640462 | 0.489 | |||
2006 | Rao R, Devgan A, Blaauw D, Sylvester D. Analytical yield prediction considering leakage/performance correlation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1685-1695. DOI: 10.1109/Tcad.2005.858351 | 0.538 | |||
2005 | Rao RR, Deogun HS, Blaauw D, Sylvester D. Bus encoding for total power reduction using a leakage-aware buffer configuration Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1376-1382. DOI: 10.1109/Tvlsi.2005.862718 | 0.481 | |||
2005 | Rao RR, Blaauw D, Sylvester D, Devgan A. Modeling and analysis of parametric yield under power and performance constraints Ieee Design and Test of Computers. 22: 376-385. DOI: 10.1109/Mdt.2005.89 | 0.527 | |||
2004 | Rao R, Srivastava A, Blaauw D, Sylvester D. Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 131-139. DOI: 10.1109/Tvlsi.2003.821549 | 0.509 | |||
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