| Year |
Citation |
Score |
| 2011 |
Keshavarzi A, Somasekhar D, Rashed M, Ahmed S, Maitra K, Miller R, Knorr A, Cho J, Augur R, Banna S, Shaw CH, Halliyal A, Schroeder U, Wei A, Egley J, et al. Architecting advanced technologies for 14nm and beyond with 3D FinFET transistors for the future SoC applications Technical Digest - International Electron Devices Meeting, Iedm. 4.1.1-4.1.4. DOI: 10.1109/IEDM.2011.6131485 |
0.315 |
|
| 2009 |
Raychowdhury A, De VK, Kurtin J, Borkar SY, Roy K, Keshavarzi A. Variation tolerance in a multichannel carbon-nanotube transistor for high-speed digital circuits Ieee Transactions On Electron Devices. 56: 383-392. DOI: 10.1109/Ted.2008.2010604 |
0.68 |
|
| 2009 |
Somasekhar D, Ye Y, Aseron P, Lu SL, Khellah MM, Howard J, Ruhl G, Karnik T, Borkar S, De VK, Keshavarzi A. 2 GHz 2 Mb 2T gain cell memory macro with 128 GBytes/sec bandwidth in a 65 nm logic process technology Ieee Journal of Solid-State Circuits. 44: 174-185. DOI: 10.1109/Jssc.2008.2007155 |
0.359 |
|
| 2008 |
Raychowdhury A, Kurtin J, Borkar S, De V, Roy K, Keshavarzi A. Theory of multi-tube carbon nanotube transistors for high speed variation-tolerant circuits Device Research Conference - Conference Digest, Drc. 23-24. DOI: 10.1109/DRC.2008.4800719 |
0.673 |
|
| 2007 |
Raychowdhury A, Kurtin J, Roy K, De V, Keshavarzi A. Digital Circuits with Carbon Nanotube Transistors The Japan Society of Applied Physics. 2007: 1162-1163. DOI: 10.7567/Ssdm.2007.J-9-1 |
0.688 |
|
| 2006 |
Raychowdhury A, Keshavarzi A, Kurtin J, De V, Roy K. Carbon nanotube field-effect transistors for high-performance digital circuits - DC analysis and modeling toward optimum transistor structure Ieee Transactions On Electron Devices. 53: 2711-2717. DOI: 10.1109/Ted.2006.883816 |
0.698 |
|
| 2006 |
Keshavarzi A, Raychowdhury A, Kurtin J, Roy K, De V. Carbon nanotube field-effect transistors for high-performance digital circuits - Transient analysis, parasitics, and scalability Ieee Transactions On Electron Devices. 53: 2718-2726. DOI: 10.1109/Ted.2006.883813 |
0.718 |
|
| 2006 |
Bota SA, Rosselló JL, De Benito C, Keshavarzi A, Segura J. Impact of thermal gradients on clock skew and testing Ieee Design and Test of Computers. 23: 414-424. DOI: 10.1109/Mdt.2006.126 |
0.364 |
|
| 2006 |
Keshavarzi A, Raychowdhury A, Kurtin J, Roy K, De V. Scalability of carbon nanotube FET-based circuits 2006 Ieee Asian Solid-State Circuits Conference, Asscc 2006. 415-418. DOI: 10.1109/ASSCC.2006.357939 |
0.686 |
|
| 2004 |
Vassighi A, Semenov O, Sachdev M, Keshavarzi A, Hawkins C. CMOS IC technology scaling and its impact on burn-in Ieee Transactions On Device and Materials Reliability. 4: 208-221. DOI: 10.1109/Tdmr.2004.826591 |
0.378 |
|
| 2004 |
Chatterjee B, Sachdev M, Keshavarzi A. DFT for delay fault testing of high-performance digital circuits Ieee Design and Test of Computers. 21: 248-258. DOI: 10.1109/Mdt.2004.10 |
0.407 |
|
| 2004 |
Chatterjee B, Sachdev M, Keshavarzi A. A DFT technique for delay fault testability and diagnostics in 32-bit high performance CMOS ALUs Proceedings - International Test Conference. 1108-1117. |
0.318 |
|
| 2003 |
Keshavarzi A, Roy K, Hawkins CF, De V. Multiple-Parameter CMOS IC Testing with Increased Sensitivity for I DDQ Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 863-870. DOI: 10.1109/Tvlsi.2003.812298 |
0.501 |
|
| 2003 |
Semenov O, Vassighi A, Sachdev M, Keshavarzi A, Hawkins CF. Effect of CMOS technology scaling on thermal management during burn-in Ieee Transactions On Semiconductor Manufacturing. 16: 686-695. DOI: 10.1109/Tsm.2003.818985 |
0.347 |
|
| 2003 |
Narendra S, Keshavarzi A, Bloechel BA, Borkar S, De V. Forward body bias for microprocessors in 130-nm technology generation and beyond Ieee Journal of Solid-State Circuits. 38: 696-701. DOI: 10.1109/Jssc.2003.810054 |
0.453 |
|
| 2003 |
Borkar S, Karnik T, Narendra S, Tschanz J, Keshavarzi A, De V. Parameter variations and impact on circuits and microarchitecture Proceedings - Design Automation Conference. 338-342. |
0.33 |
|
| 2002 |
Keshavarzi A, Tschanz JW, Narendra S, De V, Roy K, Hawkins CF, Daasch WR, Sachdev M. Leakage and process variation effects in current testing on future CMOS circuits Ieee Design and Test of Computers. 19: 36-43. DOI: 10.1109/Mdt.2002.1033790 |
0.537 |
|
| 2002 |
Hamzaoglu F, Ye Y, Keshavarzi A, Zhang K, Narendra S, Borkar S, Stan M, De V. Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 91-95. DOI: 10.1109/92.994983 |
0.416 |
|
| 2002 |
Chen Z, Wei L, Keshavarzi A, Roy K. I DDQ testing for deep-submicron ICs: Challenges and solutions Ieee Design and Test of Computers. 19: 24-33. DOI: 10.1109/54.990439 |
0.477 |
|
| 2002 |
Alorda B, Bloechel B, Keshavarzi A, Segura J. Transient current off-chip sensor circuit for digital IC production testing Electronics Letters. 38: 1028-1029. DOI: 10.1049/el:20020694 |
0.301 |
|
| 2002 |
Keshavarzi A, Narendra S, Bloechel B, Borkar S, De V. Forward body bias for microprocessors in 130nm technology generation and beyond Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 312-315. |
0.345 |
|
| 2001 |
Narendra S, Tschanz J, Keshavarzi A, Borkar S, De V. Comparative performance, leakage power and switching power of circuits in 150nm PD-SOI and bulk technologies including impact of SOI history effect Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 217-218. |
0.345 |
|
| 2000 |
Keshavarzi A, Borkar S, De V. Feasibility of current measurements in sub 0.25-micron VLSIs Proceedings - 2000 Ieee International Workshop On Defect Based Testing. 3-8. DOI: 10.1109/DBT.2000.843683 |
0.355 |
|
| 2000 |
Keshavarzi A, Roy K, Hawkins CF. Intrinsic leakage in deep submicron CMOS ICs - measurement-based test solutions Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 717-723. DOI: 10.1109/92.902266 |
0.455 |
|
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