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Arijit Raychowdhury, Ph.D. - Publications

Affiliations: 
2007 Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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80 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2022 Lele AS, Fang Y, Anwar A, Raychowdhury A. Bio-mimetic high-speed target localization with fused frame and event vision for edge application. Frontiers in Neuroscience. 16: 1010302. PMID 36507348 DOI: 10.3389/fnins.2022.1010302  0.718
2020 Xia Q, Berggren KK, Likharev K, Strukov DB, Jiang H, Mikolajick T, Querlioz D, Salinga M, Erickson J, Pi S, Xiong F, Lin P, Li C, Xiong S, Hoskins B, ... ... Raychowdhury A, et al. Roadmap on emerging hardware and technology for machine learning. Nanotechnology. PMID 32679577 DOI: 10.1088/1361-6528/Aba70F  0.486
2020 Cao N, Chang M, Raychowdhury A. A 65-nm 8-to-3-b 1.0–0.36-V 9.1–1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics Ieee Journal of Solid-State Circuits. 55: 49-59. DOI: 10.1109/Jssc.2019.2935533  0.316
2019 Golder A, Das D, Danial J, Ghosh S, Sen S, Raychowdhury A. Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack Ieee Transactions On Very Large Scale Integration Systems. 27: 2720-2733. DOI: 10.1109/Tvlsi.2019.2926324  0.336
2019 Yoon I, Khan A, Datta S, Raychowdhury A, Chang M, Ni K, Jerry M, Gangopadhyay S, Smith GH, Hamam T, Romberg J, Narayanan V. A FerroFET-Based In-Memory Processor for Solving Distributed and Iterative Optimizations via Least-Squares Method Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: 132-141. DOI: 10.1109/Jxcdc.2019.2930222  0.319
2019 Yoon I, Anwar MA, Joshi RV, Rakshit T, Raychowdhury A. Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 9: 485-497. DOI: 10.1109/Jetcas.2019.2932285  0.315
2018 Cao N, Ting J, Sen S, Raychowdhury A. Smart Sensing for HVAC Control: Collaborative Intelligence in Optical and IR Cameras Ieee Transactions On Industrial Electronics. 65: 9785-9794. DOI: 10.1109/Tie.2018.2818665  0.324
2018 Amaravati A, Xu S, Cao N, Romberg J, Raychowdhury A. A Light-Powered Smart Camera With Compressed Domain Gesture Detection Ieee Transactions On Circuits and Systems For Video Technology. 28: 3077-3085. DOI: 10.1109/Tcsvt.2017.2731767  0.363
2018 Nasir SB, Sen S, Raychowdhury A. A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-Off Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 1864-1868. DOI: 10.1109/Tcsii.2018.2816949  0.357
2018 Amaravati A, Xu S, Romberg J, Raychowdhury A. A 130 nm 165 nJ/frame Compressed-Domain Smashed-Filter-Based Mixed-Signal Classifier for “In-Sensor” Analytics in Smart Cameras Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 296-300. DOI: 10.1109/Tcsii.2017.2690861  0.316
2018 Das D, Maity S, Nasir SB, Ghosh S, Raychowdhury A, Sen S. ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity Ieee Transactions On Circuits and Systems I: Regular Papers. 65: 3300-3311. DOI: 10.1109/Tcsi.2018.2819499  0.346
2018 Jerry M, Ni K, Parihar A, Raychowdhury A, Datta S. Stochastic Insulator-to-Metal Phase Transition-Based True Random Number Generator Ieee Electron Device Letters. 39: 139-142. DOI: 10.1109/Led.2017.2771812  0.3
2018 Nasir SB, Sen S, Raychowdhury A. Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits Ieee Journal of Solid-State Circuits. 53: 569-581. DOI: 10.1109/Jssc.2017.2767183  0.378
2017 Zhang DC, Swaminathan M, Raychowdhury A, Keezer D. Enhancing the Bandwidth of Low-Dropout Regulators Using Power Transmission Lines for High-Speed I/Os Ieee Transactions On Components, Packaging and Manufacturing Technology. 7: 533-543. DOI: 10.1109/Tcpmt.2017.2655002  0.368
2016 Nasir SB, Gangopadhyay S, Raychowdhury A. All-Digital Low-Dropout Regulator With Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits Ieee Transactions On Power Electronics. 31: 8293-8302. DOI: 10.1109/Tpel.2016.2519446  0.385
2016 Venkatesan R, Kozhikkottu VJ, Sharad M, Augustine C, Raychowdhury A, Roy K, Raghunathan A. Cache Design with Domain Wall Memory Ieee Transactions On Computers. 65: 1010-1024. DOI: 10.1109/Tc.2015.2506581  0.689
2016 Chintaluri A, Naeimi H, Natarajan S, Raychowdhury A. Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays Ieee Journal On Emerging and Selected Topics in Circuits and Systems. DOI: 10.1109/Jetcas.2016.2547779  0.362
2015 Maffezzoni P, Daniel L, Shukla N, Datta S, Raychowdhury A. Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 2207-2215. DOI: 10.1109/Tcsi.2015.2452332  0.369
2015 Parihar A, Shukla N, Datta S, Raychowdhury A. Synchronization of pairwise-coupled, identical, relaxation oscillators based on metal-insulator phase transition devices: A model study Journal of Applied Physics. 117. DOI: 10.1063/1.4906783  0.327
2015 Maffezzoni P, Daniel L, Shukla N, Datta S, Raychowdhury A, Narayanan V. Modelling hysteresis in vanadium dioxide oscillators Electronics Letters. 51: 819-820. DOI: 10.1049/El.2015.0025  0.327
2014 Gangopadhyay S, Somasekhar D, Tschanz JW, Raychowdhury A. A 32 nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits Ieee Journal of Solid-State Circuits. 49: 2684-2693. DOI: 10.1109/Jssc.2014.2353798  0.367
2014 Parihar A, Shukla N, Datta S, Raychowdhury A. Exploiting synchronization properties of correlated electron devices in a non-boolean computing fabric for template matching Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 4: 450-459. DOI: 10.1109/Jetcas.2014.2361069  0.389
2014 Tokunaga C, Ryan JF, Augustine C, Kulkarni JP, Shih YC, Kim ST, Jain R, Bowman K, Raychowdhury A, Khellah MM, Tschanz JW, De V. 5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 57: 108-109. DOI: 10.1109/ISSCC.2014.6757359  0.689
2014 Alam SM, Budnik MM, Wright PJ, Raychowdhury A, Joshi R, Chatterjee P, Wesling P, Iranmanesh AA. Welcome to ISQED 2014 Proceedings - International Symposium On Quality Electronic Design, Isqed. DOI: 10.1109/ISQED.2014.6783290  0.529
2013 Raychowdhury A, Tokunaga C, Beltman W, Deisher M, Tschanz JW, De V. A 2.3 nJ/frame voice activity detector-based audio front-end for context-aware system-on-chip applications in 32-nm CMOS Ieee Journal of Solid-State Circuits. 48: 1963-1969. DOI: 10.1109/Jssc.2013.2258827  0.402
2012 Venkatesan R, Kozhikkottu V, Augustine C, Raychowdhury A, Roy K, Raghunathan A. TapeCache: A high density, energy efficient cache based on domain wall memory Proceedings of the International Symposium On Low Power Electronics and Design. 185-190. DOI: 10.1145/2333660.2333707  0.645
2011 Augustine C, Raychowdhury A, Somasekhar D, Tschanz J, De V, Roy K. Design space exploration of typical STT MTJ stacks in memory arrays in the presence of variability and disturbances Ieee Transactions On Electron Devices. 58: 4333-4343. DOI: 10.1109/Ted.2011.2169962  0.671
2011 Bowman KA, Tokunaga C, Tschanz JW, Raychowdhury A, Khellah MM, Geuskens BM, Lu SLL, Aseron PA, Karnik T, De VK. All-digital circuit-level dynamic variation monitor for silicon debug and adaptive clock control Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 2017-2025. DOI: 10.1109/Tcsi.2011.2163893  0.366
2011 Raychowdhury A, Geuskens BM, Bowman KA, Tschanz JW, Lu SLL, Karnik T, Khellah MM, De VK. Tunable replica bits for dynamic variation tolerance in 8T SRAM arrays Ieee Journal of Solid-State Circuits. 46: 797-805. DOI: 10.1109/Jssc.2011.2108141  0.318
2011 Bowman KA, Tschanz JW, Lu SLL, Aseron PA, Khellah MM, Raychowdhury A, Geuskens BM, Tokunaga C, Wilkerson CB, Karnik T, De VK. A 45 nm resilient microprocessor core for dynamic variation tolerance Ieee Journal of Solid-State Circuits. 46: 194-208. DOI: 10.1109/Jssc.2010.2089657  0.36
2011 Raychowdhury A, Tschanz J, Bowman K, Lu SL, Aseron P, Khellah M, Geuskens B, Tokunaga C, Wilkerson C, Karnik T, De V. Error detection and correction in microprocessor core and memory due to fast dynamic voltage droops Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 208-217. DOI: 10.1109/Jetcas.2011.2167070  0.345
2011 Augustine C, Raychowdhury A, Behin-Aein B, Srinivasan S, Tschanz J, De VK, Roy K. Numerical analysis of domain wall propagation for dense memory arrays Technical Digest - International Electron Devices Meeting, Iedm. 17.6.1-17.6.4. DOI: 10.1109/IEDM.2011.6131575  0.614
2011 Raychowdhury A, Augustine C, Somasekhar D, Tschanz J, Roy K, De V. Numerical analysis of a novel MTJ stack for high readability and writability European Solid-State Device Research Conference. 347-350. DOI: 10.1109/ESSDERC.2011.6044163  0.612
2010 Gupta SK, Raychowdhury A, Roy K. Digital computation in subthreshold region for ultralow-power operation: A device-circuit-architecture codesign perspective Proceedings of the Ieee. 98: 160-190. DOI: 10.1109/JPROC.2009.2035060  0.631
2010 Raychowdhury A, Geuskens B, Kulkarni J, Tschanz J, Bowman K, Karnik T, Lu SL, De V, Khellah MM. PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 352-353. DOI: 10.1109/ISSCC.2010.5433815  0.606
2010 Augustine C, Raychowdhury A, Somasekhar D, Tschanz J, Roy K, De VK. Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays Technical Digest - International Electron Devices Meeting, Iedm. 22.7.1-22.7.4. DOI: 10.1109/IEDM.2010.5703416  0.621
2010 Tschanz J, Bowman K, Khellah M, Wilkerson C, Geuskens B, Somasekhar D, Raychowdhury A, Kulkarni J, Tokunaga C, Lu SL, Karnik T, De V. Resilient design in scaled CMOS for energy efficiency Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 625. DOI: 10.1109/ASPDAC.2010.5419812  0.608
2009 Raychowdhury A, De VK, Kurtin J, Borkar SY, Roy K, Keshavarzi A. Variation tolerance in a multichannel carbon-nanotube transistor for high-speed digital circuits Ieee Transactions On Electron Devices. 56: 383-392. DOI: 10.1109/Ted.2008.2010604  0.668
2009 Lakdawala H, Li YW, Raychowdhury A, Taylor G, Soumyanath K. A 1.05 V 1.6 mW, 0.45 °C 3φ Resolution ΣΔ based temperature sensor with parasitic resistance compensation in 32 nm digital CMOS process Ieee Journal of Solid-State Circuits. 44: 3621-3630. DOI: 10.1109/Jssc.2009.2035553  0.305
2009 Augustine C, Raychowdhury A, Gao Y, Lundstrom M, Roy K. PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 80-85. DOI: 10.1109/ISQED.2009.4810273  0.663
2009 Gupta SK, Raychowdhury A, Roy K. Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy Journal of Applied Physics. 105. DOI: 10.1063/1.3123763  0.621
2008 Coker A, Taylor V, Bhaduri D, Shukla S, Raychowdhury A, Roy K. Multijunction fault-tolerance architecture for nanoscale crossbar memories Ieee Transactions On Nanotechnology. 7: 202-208. DOI: 10.1109/Tnano.2007.911319  0.442
2008 Raychowdhury A, Kurtin J, Borkar S, De V, Roy K, Keshavarzi A. Theory of multi-tube carbon nanotube transistors for high speed variation-tolerant circuits Device Research Conference - Conference Digest, Drc. 23-24. DOI: 10.1109/DRC.2008.4800719  0.634
2008 Bhunia S, Mahmoodi H, Raychowdhury A, Roy K. Arbitrary two-pattern delay testing using a low-overhead supply gating technique Journal of Electronic Testing: Theory and Applications (Jetta). 24: 577-590. DOI: 10.1007/S10836-008-5072-4  0.629
2007 Raychowdhury A, Kurtin J, Roy K, De V, Keshavarzi A. Digital Circuits with Carbon Nanotube Transistors The Japan Society of Applied Physics. 2007: 1162-1163. DOI: 10.7567/Ssdm.2007.J-9-1  0.666
2007 Hwang ME, Raychowdhury A, Kim K, Roy K. A 85mV 40nW process-tolerant subthreshold 8×8 FIR filter in 13nm technology Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 154-155. DOI: 10.1109/VLSIC.2007.4342695  0.42
2007 Raychowdhury A, Roy K. Carbon nanotube electronics: Design of high-performance and low-power digital circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 54: 2391-2401. DOI: 10.1109/Tcsi.2007.907799  0.557
2006 Raychowdhury A, Xuanyao F, Qikai C, Roy K. Analysis of super cut-off transistors for ultralow power digital logic circuits Proceedings of the International Symposium On Low Power Electronics and Design. 2006: 2-7. DOI: 10.1145/1165573.1165577  0.451
2006 Budnik M, Raychowdhury A, Bansal A, Roy K. A high density, carbon nanotube capacitor for decoupling applications Proceedings - Design Automation Conference. 935-938. DOI: 10.1145/1146909.1147146  0.688
2006 Banerjee N, Raychowdhury A, Roy K, Bhunia S, Mahmoodi H. Novel low-overhead operand isolation techniques for low-power datapath synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1034-1039. DOI: 10.1109/Tvlsi.2006.884054  0.703
2006 Raychowdhury A, Keshavarzi A, Kurtin J, De V, Roy K. Carbon nanotube field-effect transistors for high-performance digital circuits - DC analysis and modeling toward optimum transistor structure Ieee Transactions On Electron Devices. 53: 2711-2717. DOI: 10.1109/Ted.2006.883816  0.693
2006 Keshavarzi A, Raychowdhury A, Kurtin J, Roy K, De V. Carbon nanotube field-effect transistors for high-performance digital circuits - Transient analysis, parasitics, and scalability Ieee Transactions On Electron Devices. 53: 2718-2726. DOI: 10.1109/Ted.2006.883813  0.71
2006 Ghosh S, Bhunia S, Raychowdhury A, Roy K. A novel delay fault testing methodology using low-overhead built-in delay sensor Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2934-2943. DOI: 10.1109/Tcad.2006.882523  0.704
2006 Raychowdhury A, Roy K. Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 58-65. DOI: 10.1109/Tcad.2005.853702  0.518
2006 Agarwal A, Mukhopadhyay S, Raychowdhury A, Roy K, Kim CH. Leakage power analysis and reduction for nanoscale circuits Ieee Micro. 26: 68-80. DOI: 10.1109/Mm.2006.39  0.646
2006 Ghosh S, Bhunia S, Raychowdhury A, Roy K. Delay fault localization in test-per-scan BIST using built-in delay sensor Proceedings - Iolts 2006: 12th Ieee International On-Line Testing Symposium. 2006: 31-36. DOI: 10.1109/IOLTS.2006.19  0.575
2006 Raychowdhury A, Kim JI, Peroulis D, Roy K. Integrated MEMS switches for leakage control of battery operated systems Proceedings of the Custom Integrated Circuits Conference. 457-460. DOI: 10.1109/CICC.2006.320821  0.443
2006 Keshavarzi A, Raychowdhury A, Kurtin J, Roy K, De V. Scalability of carbon nanotube FET-based circuits 2006 Ieee Asian Solid-State Circuits Conference, Asscc 2006. 415-418. DOI: 10.1109/ASSCC.2006.357939  0.671
2006 Budnik M, Raychowdhury A, Roy K. Power delivery for nanoscale processors with single wall carbon nanotube interconnects 2006 6th Ieee Conference On Nanotechnology, Ieee-Nano 2006. 2: 433-436.  0.636
2005 Raychowdhury A, Paul BC, Bhunia S, Roy K. Computing with subthreshold leakage: Device/circuit/architecture co-design for ultralow-power subthreshold operation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1213-1223. DOI: 10.1109/Tvlsi.2005.859590  0.648
2005 Raychowdhury A, Roy K. Carbon-nanotube-based voltage-mode multiple-valued logic design Ieee Transactions On Nanotechnology. 4: 168-179. DOI: 10.1109/Tnano.2004.842068  0.557
2005 Paul BC, Raychowdhury A, Roy K. Device optimization for digital subthreshold logic operation Ieee Transactions On Electron Devices. 52: 237-247. DOI: 10.1109/Ted.2004.842538  0.559
2005 Hwang ME, Raychowdhury A, Roy K. Energy-recovery techniques to reduce on-chip power density in molecular nanotechnologies Ieee Transactions On Circuits and Systems I: Regular Papers. 52: 1580-1589. DOI: 10.1109/Tcsi.2005.851692  0.649
2005 Mukhopadhyay S, Raychowdhury A, Roy K. Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 363-381. DOI: 10.1109/Tcad.2004.842810  0.653
2005 Raychowdhury A, Guo J, Roy K, Lundstrom M. Design of a novel three-valued static memory using schottky barrier carbon nanotube FETs 2005 5th Ieee Conference On Nanotechnology. 2: 695-698. DOI: 10.1109/NANO.2005.1500812  0.47
2005 Raychowdhury A, Ghosh S, Roy K. A novel on-chip delay measurement hardware for efficient speed-binning Proceedings - 11th Ieee International On-Line Testing Symposium, Iolts 2005. 2005: 287-292. DOI: 10.1109/IOLTS.2005.10  0.503
2005 Raychowdhury A, Mukhopadhyay S, Roy K. A feasibility study of subthreshold SRAM across technology generations Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 417-422. DOI: 10.1109/ICCD.2005.7  0.449
2005 Raychowdhury A, Ghosh S, Bhunia S, Ghosh D, Roy K. A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points Proceedings of the 10th Ieee European Test Symposium, Ets 2005. 2005: 108-113. DOI: 10.1109/ETS.2005.2  0.577
2005 Bhunia S, Mahmoodi H, Raychowdhury A, Roy K. A novel low-overhead delay testing technique for arbitrary two-pattern test application Proceedings -Design, Automation and Test in Europe, Date '05. 1136-1141. DOI: 10.1109/DATE.2005.27  0.619
2005 Mukhopadhyay S, Raychowdhury A, Mahmoodi H, Roy K. Leakage current based stabilization scheme for robust sense-amplifier design for yield enhancement in nano-scale SRAM Proceedings of the Asian Test Symposium. 2005: 176-181. DOI: 10.1109/ATS.2005.73  0.456
2005 Agarwal A, Mukhopadhyay S, Kim CH, Raychowdhury A, Roy K. Leakage power analysis and reduction: Models, estimation and tools Iee Proceedings: Computers and Digital Techniques. 152: 353-368. DOI: 10.1049/ip-cdt:20045084  0.482
2005 Bhunia S, Raychowdhury A, Roy K. Frequency specification testing of analog filters using wavelet transform of dynamic supply current Journal of Electronic Testing: Theory and Applications (Jetta). 21: 243-255. DOI: 10.1007/s10836-005-6354-8  0.552
2005 Bhunia S, Raychowdhury A, Roy K. Defect oriented testing of analog circuits using wavelet analysis of dynamic supply current Journal of Electronic Testing: Theory and Applications (Jetta). 21: 147-159. DOI: 10.1007/S10836-005-6144-3  0.624
2004 Raychowdhury A, Mukhopadhyay S, Roy K. A circuit-compatible model of ballistic carbon nanotube field-effect transistors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1411-1420. DOI: 10.1109/Tcad.2004.835135  0.658
2004 Raychowdhury A, Roy K. A circuit model for carbon nanotube interconnects: Comparative study with Cu interconnects for scaled technologies Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 237-240. DOI: 10.1109/ICCAD.2004.1382578  0.462
2004 Bhunia S, Raychowdhury A, Roy K. Trim bit setting of analog filters using wavelet-based supply current analysis Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 708-709. DOI: 10.1109/DATE.2004.1268941  0.56
2004 Hwang ME, Raychowdhury A, Roy K. Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies Proceedings - Ieee International Symposium On Circuits and Systems. 3: III709-III712.  0.31
2004 Raychowdhury A, Guo J, Roy K, Lundstrom M. Choice of flat-band voltage, V DD and diameter of ambipolar schottky-barrier carbon nanotube transistors in digital circuit design 2004 4th Ieee Conference On Nanotechnology. 311-313.  0.343
2003 Raychowdhury A, Mukhopadhyay S, Roy K. Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance Proceedings of the Ieee Conference On Nanotechnology. 1: 343-346. DOI: 10.1109/NANO.2003.1231788  0.495
2003 Raychowdhury A, Mukhopadhyay S, Roy K. Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 487-490.  0.3
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