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Debabrata Mohapatra, Ph.D. - Publications

Affiliations: 
2011 Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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5 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Chippa VK, Mohapatra D, Roy K, Chakradhar ST, Raghunathan A. Scalable effort hardware design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2004-2016. DOI: 10.1109/Tvlsi.2013.2276759  0.489
2013 Gupta V, Mohapatra D, Raghunathan A, Roy K. Low-Power Digital Signal Processing Using Approximate Adders Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 124-137. DOI: 10.1109/Tcad.2012.2217962  0.519
2013 Chippa VK, Jayakumar H, Mohapatra D, Roy K, Raghunathan A. Energy-efficient recognition and mining processor using scalable effort design Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2013.6658433  0.421
2011 Chang IJ, Mohapatra D, Roy K. A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications Ieee Transactions On Circuits and Systems For Video Technology. 21: 101-112. DOI: 10.1109/Tcsvt.2011.2105550  0.574
2010 Ghosh S, Mohapatra D, Karakonstantis G, Roy K. Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1301-1309. DOI: 10.1109/Tvlsi.2009.2022531  0.556
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