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Jintae Kim - Publications

Affiliations: 
2008 University of California, Los Angeles, Los Angeles, CA 
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21 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Jin J, Jin X, Jung J, Kwon K, Kim J, Chun J. A 0.75–3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector Ieee Journal of Solid-State Circuits. 53: 2994-3003. DOI: 10.1109/Jssc.2018.2856243  0.357
2018 Park H, Kim J. A 0.8-V Resistor-Based Temperature Sensor in 65-nm CMOS With Supply Sensitivity of 0.28 °C/V Ieee Journal of Solid-State Circuits. 53: 906-912. DOI: 10.1109/Jssc.2017.2788878  0.353
2017 Joo S, Kim J, Kim S. Power-Supply Rejection Model Analysis of Capacitor-Less LDO Regulator Designs Ieice Transactions On Electronics. 100: 504-512. DOI: 10.1587/Transele.E100.C.504  0.334
2016 Park Y, Kim J, Kim C. A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs Ieee Transactions On Circuits and Systems. 63: 1889-1897. DOI: 10.1109/Tcsi.2016.2593927  0.397
2016 Jang I, Lee Y, Kim S, Kim J. Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization Ieee Transactions On Circuits and Systems I: Regular Papers. 63: 540-550. DOI: 10.1109/Tcsi.2016.2528481  0.401
2015 Jin X, Bae JH, Chun JH, Kim J, Kwon KW. A 1.25 GHz low power multi-phase PLL using phase interpolation between two complementary clocks Journal of Semiconductor Technology and Science. 15: 594-600. DOI: 10.5573/Jsts.2015.15.6.594  0.318
2015 Joo S, Kim J, Kim S. Stability and PSR(Power-Supply Rejection) Models for Design Optimization of Capacitor-less LDO Regulators The Journal of Korean Institute of Electromagnetic Engineering and Science. 26: 71-80. DOI: 10.5515/Kjkiees.2015.26.1.71  0.358
2015 Lee H, Aurangozeb, Park S, Kim J, Kim C. A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter Ieee Transactions On Very Large Scale Integration Systems. 23: 2371-2383. DOI: 10.1109/Tvlsi.2014.2372033  0.469
2015 Kim J, Modjtahedi S, Yang CKK. A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2395-2407. DOI: 10.1109/Tvlsi.2014.2370042  0.694
2015 Kim J, Lee M. A Semiblind Digital-Domain Calibration of Pipelined A/D Converters via Convex Optimization Ieee Transactions On Very Large Scale Integration Systems. 23: 1375-1379. DOI: 10.1109/Tvlsi.2014.2336472  0.357
2015 Jang I, Kim J, Kim S. Accurate delay models of CMOS CML circuits for design optimization Analog Integrated Circuits and Signal Processing. 82: 297-307. DOI: 10.1007/S10470-014-0460-4  0.389
2014 Jang I, Kim J, Kim S. Design Optimization of CML-Based High-Speed Digital Circuits Journal of the Institute of Electronics Engineers of Korea. 51: 57-65. DOI: 10.5573/Ieie.2014.51.11.057  0.379
2014 Kim J, Modjtahedi S, Yang CKK. Flexible-assignment calibration technique for mismatch-constrained digital-to-analog converters Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1934-1944. DOI: 10.1109/Tvlsi.2013.2279133  0.693
2013 Song H, Kim J, Lee M. A low-power reference buffer with high PSRR and low crosstalk for time-interleaved ADCs Ieice Electronics Express. 10: 20130482-20130482. DOI: 10.1587/Elex.10.20130482  0.307
2013 Kim J, Park CS. A Calibration Technique for Multibit Stage Pipelined A/D Converters via Least-Squares Method Ieee Transactions On Instrumentation and Measurement. 62: 3390-3392. DOI: 10.1109/Tim.2013.2282184  0.36
2013 Kim J. A convex macromodeling of dynamic comparator for analog circuit synthesis Analog Integrated Circuits and Signal Processing. 77: 299-305. DOI: 10.1007/S10470-013-0181-0  0.372
2012 Moon J, Jung W, Kim J, Kwon K, Jun Y, Chun J. (A 2.0-GS/s 5-b Current Mode ADC-Based Receiver with Embedded Channel Equalizer ) Journal of the Institute of Electronics Engineers of Korea. 49: 184-193. DOI: 10.5573/Ieek.2012.49.12.184  0.414
2011 Kim J, Limotyrakis S, Yang CKK. Multilevel power optimization of pipelined A/D converters Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 832-845. DOI: 10.1109/Tvlsi.2010.2041077  0.435
2011 Kim J, Jhaveri R, Woo JCS, Yang CKK. Circuit-level performance evaluation of schottky tunneling transistor in mixed-signal applications Ieee Transactions On Nanotechnology. 10: 291-299. DOI: 10.1109/Tnano.2009.2039646  0.385
2010 Kim J, Vandenberghe L, Yang CKK. Convex piecewise-linear modeling method for circuit optimization via geometric programming Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1823-1827. DOI: 10.1109/Tcad.2010.2053151  0.348
2007 Kim J, Hatamkhani H, Yang CKK. A large-swing transformer-boosted serial link transmitter with > v DD swing Ieee Journal of Solid-State Circuits. 42: 1131-1142. DOI: 10.1109/Jssc.2007.894821  0.666
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