Kundan Nepal, Ph.D.

Affiliations: 
2007 Brown University, Providence, RI 
Area:
Computer Architecture, Low-Power Design, and Computer-Aided VLSI Design.
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"Kundan Nepal"

Parents

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Ruth Iris Bahar grad student 2007 Brown
 (Designing reliable nanoscale circuits using principles of Markov random fields.)
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Publications

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Hellkamp D, Nepal K. (2019) True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors Journal of Circuits, Systems, and Computers. 28: 1950085
Sun Y, Zhang F, Jiang H, et al. (2019) Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack Journal of Electronic Testing. 35: 887-900
Nepal K, Alhelaly S, Dworak J, et al. (2015) Repairing a 3-D die-stack using available programmable logic Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 849-861
Hellkamp D, Nepal K. (2015) Metallic tube-tolerant ternary dynamic content-addressable memory based on carbon nanotube transistors Micro & Nano Letters. 10: 209-212
Dworak J, Nepal K, Alves N, et al. (2013) Using implications to choose tests through suspect fault identification Acm Transactions On Design Automation of Electronic Systems. 18: 14
Nepal K, You K. (2012) Carbon nanotube field effect transistor-based content addressable memory architectures Micro & Nano Letters. 7: 20-23
Dunbar C, Nepal K. (2011) Using platform FPGAs for fault emulation and test-set generation to detect stuck-at faults Journal of Computers. 6: 2335-2344
You K, Nepal K. (2011) Design of a ternary static memory cell using carbon nanotube-based transistors Micro & Nano Letters. 6: 381-385
Alves N, Buben A, Nepal K, et al. (2010) A cost effective approach for online error detection using invariant relationships Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 788-801
Nepal K, Bahar RI, Mundy J, et al. (2007) Designing nanoscale logic circuits based on Markov random fields Journal of Electronic Testing: Theory and Applications (Jetta). 23: 255-266
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