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Andy K. Chao, Ph.D.

Affiliations: 
2007 Stanford University, Palo Alto, CA 
Area:
Electronics and Electrical Engineering
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Yoshio Nishi grad student 2007 Stanford
 (Low-power nanoelectronic device design and a resulting power optimization methodology.)

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Publications

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Chao AK, Kapur P, Morifuji E, et al. (2007) Electro-thermally coupled power optimization for future transistors 65th Drc Device Research Conference. 79-80
Chao AK, Kapur P, Shenoy RS, et al. (2005) Incorporation of supply voltage and process variations in the power optimization for future transistors Device Research Conference - Conference Digest, Drc. 2005: 95-96
Kapur P, Shenoy RS, Chao AK, et al. (2004) Power optimization of future transistors and a resulting global comparison standard Technical Digest - International Electron Devices Meeting, Iedm. 415-418
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