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Christopher L. Ayala, Ph.D. - Publications

Affiliations: 
2012 Computer Engineering Stony Brook University, Stony Brook, NY, United States 
Area:
Parallel computer architecture; high-performance systems design; superconductor processors
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26 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Fourie CJ, Ayala CL, Schindler L, Tanaka T, Yoshikawa N. Design and Characterization of Track Routing Architecture for RSFQ and AQFP Circuits in a Multilayer Process Ieee Transactions On Applied Superconductivity. 30: 1-9. DOI: 10.1109/Tasc.2020.2988876  0.589
2020 Ayala CL, Saito R, Tanaka T, Chen O, Takeuchi N, He Y, Yoshikawa N. A semi-custom design methodology and environment for implementing superconductor adiabatic quantum-flux-parametron microprocessors Superconductor Science and Technology. 33: 54006. DOI: 10.1088/1361-6668/Ab7Ec3  0.476
2020 He Y, Ayala CL, Takeuchi N, Yamae T, Hironaka Y, Sahu A, Gupta V, Talalaevskii A, Gupta D, Yoshikawa N. A compact AQFP logic cell design using an 8-metal layer superconductor process Superconductor Science and Technology. 33: 35010. DOI: 10.1088/1361-6668/Ab6Feb  0.449
2019 Takeuchi N, Aono M, Hara-Azumi Y, Ayala CL. A Circuit-Level Amoeba-Inspired SAT Solver Ieee Transactions On Circuits and Systems Ii-Express Briefs. 1-1. DOI: 10.1109/Tcsii.2019.2951181  0.46
2019 Chen O, Saito R, Tanaka T, Ayala CL, Takeuchi N, Yoshikawa N. Design of Adiabatic Quantum-Flux-Parametron Register Files Using a Top-Down Design Flow Ieee Transactions On Applied Superconductivity. 29: 1-5. DOI: 10.1109/Tasc.2019.2908277  0.647
2019 Takeuchi N, Ayala CL, Chen O, Yoshikawa N. A Feedback-Friendly Large-Scale Clocking Scheme for Adiabatic Quantum-Flux-Parametron Logic Datapaths Ieee Transactions On Applied Superconductivity. 29: 1-5. DOI: 10.1109/Tasc.2019.2904480  0.54
2019 Tanaka T, Ayala CL, Xu Q, Saito R, Yoshikawa N. Fabrication of Adiabatic Quantum-Flux-Parametron Integrated Circuits Using an Automatic Placement Tool Based on Genetic Algorithms Ieee Transactions On Applied Superconductivity. 29: 1-6. DOI: 10.1109/Tasc.2019.2900220  0.65
2019 Fourie CJ, Law M, Wang Y, Annavaram M, Beerel P, Gupta S, Nazarian S, Pedram M, Jackman K, Botha MM, Razmkhah S, Febvre P, Ayala CL, Xu Q, Yoshikawa N, et al. ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress Ieee Transactions On Applied Superconductivity. 29: 1-7. DOI: 10.1109/Tasc.2019.2892115  0.58
2019 Takeuchi N, Yamae T, Ayala CL, Suzuki H, Yoshikawa N. An adiabatic superconductor 8-bit adder with 24kBT energy dissipation per junction Applied Physics Letters. 114: 42602. DOI: 10.1063/1.5080753  0.573
2017 Murai Y, Ayala CL, Takeuchi N, Yamanashi Y, Yoshikawa N. Development and Demonstration of Routing and Placement EDA Tools for Large-Scale Adiabatic Quantum-Flux-Parametron Circuits Ieee Transactions On Applied Superconductivity. 27: 1-9. DOI: 10.1109/Tasc.2017.2721965  0.602
2017 Xu Q, Ayala CL, Takeuchi N, Murai Y, Yamanashi Y, Yoshikawa N. Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation With HDL Back-End Verification Ieee Transactions On Applied Superconductivity. 27: 1-5. DOI: 10.1109/Tasc.2017.2662017  0.627
2017 Tsuji N, Ayala CL, Takeuchi N, Ortlepp T, Yamanashi Y, Yoshikawa N. Design and Implementation of a 16-Word by 1-Bit Register File Using Adiabatic Quantum Flux Parametron Logic Ieee Transactions On Applied Superconductivity. 27: 1-4. DOI: 10.1109/Tasc.2017.2656128  0.691
2017 Ayala CL, Takeuchi N, Yamanashi Y, Ortlepp T, Yoshikawa N. Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic Ieee Transactions On Applied Superconductivity. 27: 1-7. DOI: 10.1109/Tasc.2016.2642041  0.682
2016 Xu Q, Ayala CL, Takeuchi N, Yamanashi Y, Yoshikawa N. HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic Ieee Transactions On Applied Superconductivity. 26: 1-5. DOI: 10.1109/Tasc.2016.2615123  0.492
2015 Dorojevets M, Chen Z, Ayala CL, Kasperek AK. Towards 32-bit energy-efficient superconductor RQL processors: The cell-level design and analysis of key processing and on-chip storage units Ieee Transactions On Applied Superconductivity. 25. DOI: 10.1109/Tasc.2014.2368354  0.65
2015 Ayala CL, Bazigos A, Grogg D, Pu Y, Hagleitner C. Ultra-low-energy adiabatic dynamic logic circuits using nanoelectromechanical switches Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 2596-2599. DOI: 10.1109/ISCAS.2015.7169217  0.416
2015 Ayala CL, Grogg D, Bazigos A, Bleiker SJ, Fernandez-Bolaños M, Niklaus F, Hagleitner C. Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts Solid-State Electronics. 113: 157-166. DOI: 10.1016/J.Sse.2015.05.029  0.471
2014 Bazigos A, Ayala CL, Fernandez-Bolaños M, Pu Y, Grogg D, Hagleitner C, Rana S, Qin TT, Pamunuwa D, Ionescu AM. Analytical compact model in verilog - A for electrostatically actuated ohmic switches Ieee Transactions On Electron Devices. 61: 2186-2194. DOI: 10.1109/Ted.2014.2318199  0.383
2014 Rana S, Qin T, Bazigos A, Grogg D, Despont M, Ayala CL, Hagleitner C, Ionescu AM, Canegallo R, Pamunuwa D. Energy and latency optimization in NEM relay-based digital circuits Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 2348-2359. DOI: 10.1109/Tcsi.2014.2309752  0.513
2014 Ayala CL, Grogg D, Bazigos A, Badia MFB, Duerig UT, Despont M, Hagleitner C. A 6.7 MHz nanoelectromechanical ring oscillator using curved cantilever switches coated with amorphous carbon European Solid-State Device Research Conference. 66-69. DOI: 10.1109/ESSDERC.2014.6948759  0.342
2014 Bazigos A, Ayala CL, Rana S, Grogg D, Fernandez-Bolaños M, Hagleitner C, Qin T, Pamunuwa D, Ionescu AM. Electromechanical design space exploration for electrostatically actuated ohmic switches using extended parallel plate compact model Solid-State Electronics. 99: 93-100. DOI: 10.1016/J.Sse.2014.06.030  0.455
2013 Dorojevets M, Ayala CL, Yoshikawa N, Fujimaki A. 16-Bit wave-pipelined sparse-tree RSFQ adder Ieee Transactions On Applied Superconductivity. 23. DOI: 10.1109/Tasc.2012.2233846  0.787
2013 Dorojevets M, Ayala CL, Yoshikawa N, Fujimaki A. 8-bit asynchronous sparse-tree superconductor RSFQ arithmetic-logic unit with a rich set of operations Ieee Transactions On Applied Superconductivity. 23. DOI: 10.1109/Tasc.2012.2229334  0.788
2012 Filippov TV, Sahu A, Kirichenko AF, Vernik IV, Dorojevets M, Ayala CL, Mukhanov OA. 20 GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit Physics Procedia. 36: 59-65. DOI: 10.1016/J.Phpro.2012.06.130  0.803
2011 Filippov T, Dorojevets M, Sahu A, Kirichenko A, Ayala C, Mukhanov O. 8-bit asynchronous wave-pipelined RSFQ Arithmetic-Logic Unit Ieee Transactions On Applied Superconductivity. 21: 847-851. DOI: 10.1109/Tasc.2010.2103918  0.81
2011 Dorojevets M, Ayala CL, Kasperek AK. Data-flow microarchitecture for wide datapath rsfq processors: Design study Ieee Transactions On Applied Superconductivity. 21: 787-791. DOI: 10.1109/Tasc.2010.2087410  0.657
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