☰

Peter A. Beerel - Publications

Affiliations: 
Electrical Engineering(VLSI Design) University of Southern California, Los Angeles, CA, United States 
Area:
Electronics and Electrical Engineering
Tree Info Similar researchers PubMed Report error

41 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Tadros RN, Beerel PA. A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures Acm Transactions On Design Automation of Electronic Systems. 25: 1-28. DOI: 10.1145/3373355  0.311
2020 Aketi SA, Gupta S, Cheng H, Mekie J, Beerel PA. SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol Ieee Transactions On Circuits and Systems I-Regular Papers. 67: 1667-1677. DOI: 10.1109/Tcsi.2020.2965073  0.487
2020 Datta G, Sudheer AS, Srinivas PH, Beerel PA. Single Flux Quantum (SFQ) First-in-First-Out (FIFO) Synchronizers: New Designs and Paradigms Ieee Transactions On Applied Superconductivity. 30: 1-8. DOI: 10.1109/Tasc.2020.2997260  0.312
2020 Tadros RN, Fayyazi A, Pedram M, Beerel PA. SystemVerilog Modeling of SFQ and AQFP Circuits Ieee Transactions On Applied Superconductivity. 30: 1-13. DOI: 10.1109/Tasc.2019.2957196  0.511
2020 Tadros RN, Beerel PA. Optimizing (HC) $^2$ LC, A Robust Clock Distribution Network For SFQ Circuits Ieee Transactions On Applied Superconductivity. 30: 1-11. DOI: 10.1109/Tasc.2019.2933366  0.484
2019 Cheng H, Wang H, Zhang M, Hand D, Beerel PA. Automatic Retiming of Two-Phase Latch-Based Resilient Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1305-1316. DOI: 10.1109/Tcad.2018.2846631  0.529
2019 Fourie CJ, Law M, Wang Y, Annavaram M, Beerel P, Gupta S, Nazarian S, Pedram M, Jackman K, Botha MM, Razmkhah S, Febvre P, Ayala CL, Xu Q, Yoshikawa N, et al. ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress Ieee Transactions On Applied Superconductivity. 29: 1-7. DOI: 10.1109/Tasc.2019.2892115  0.502
2019 Zhang Y, Li J, Cheng H, Zha H, Draper J, Beerel PA. Yield modelling and analysis of bundled data and ring-oscillator based designs Iet Computers and Digital Techniques. 13: 262-272. DOI: 10.1049/Iet-Cdt.2018.5040  0.492
2018 Moreira MT, Beerel PA, Sartori MLL, Calazans NLV. NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 1981-1993. DOI: 10.1109/Tcsi.2017.2772206  0.557
2018 Huang H, Cheng H, Chu C, Beerel PA. Area Optimization of Timing Resilient Designs Using Resynthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1197-1210. DOI: 10.1109/Tcad.2017.2748001  0.455
2018 Tadros RN, Beerel PA. A Robust and Self-Adaptive Clocking Technique for SFQ Circuits Ieee Transactions On Applied Superconductivity. 28: 1-11. DOI: 10.1109/Tasc.2018.2856836  0.518
2017 Singhvi A, Moreira MT, Tadros RN, Calazans NLV, Beerel PA. A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits Acm Journal On Emerging Technologies in Computing Systems. 13: 15. DOI: 10.1145/2948067  0.511
2017 Saifhashemi A, Huang H, Beerel PA. Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 265-278. DOI: 10.1109/Tcad.2016.2571840  0.583
2016 Tadros RN, Hua W, Moreira MT, Calazans NLV, Beerel PA. A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI Ieee Transactions On Circuits and Systems Ii-Express Briefs. 63: 858-862. DOI: 10.1109/Tcsii.2016.2536179  0.475
2016 Zhang Y, Heck LS, Moreira MT, Zar D, Breuer MA, Calazans NLV, Beerel PA. Testable MUTEX Design Ieee Transactions On Circuits and Systems I: Regular Papers. 63: 1188-1199. DOI: 10.1109/Tcsi.2016.2561906  0.462
2016 Tadros R, Dasari N, Beerel P. Ultra-low power pass-transistor-logic-based delay line design for sub-threshold applications Electronics Letters. 52: 1910-1912. DOI: 10.1049/El.2016.3240  0.521
2015 Hua W, Tadros RN, Beerel P. 2 ps resolution, fine-grained delay element in 28 nm FDSOI Electronics Letters. 51: 1848-1850. DOI: 10.1049/El.2015.2667  0.341
2014 Golani P, Beerel PA. Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template Ieee Transactions On Very Large Scale Integration Systems. 22: 838-849. DOI: 10.1109/Tvlsi.2013.2257187  0.416
2014 Dimou GD, Beerel PA, Lines AM. Performance-driven clustering of asynchronous circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 197-209. DOI: 10.1109/Tcad.2013.2287189  0.505
2011 Stevens KS, Golani P, Beerel PA. Energy and Performance Models for Synchronous and Asynchronous Communication Ieee Transactions On Very Large Scale Integration Systems. 19: 369-382. DOI: 10.1109/Tvlsi.2009.2037327  0.461
2011 Beerel PA, Dimou GD, Lines AM. Proteus: An ASIC flow for GHz asynchronous designs Ieee Design and Test of Computers. 28: 36-50. DOI: 10.1109/Mdt.2011.114  0.461
2007 Beerel PA, Roncken ME. Low Power and Energy Efficient Asynchronous Design Journal of Low Power Electronics. 3: 234-253. DOI: 10.1166/Jolpe.2007.138  0.368
2006 Golani P, Beerel PA. Back-Annotation in High-Speed Asynchronous Design Journal of Low Power Electronics. 2: 37-44. DOI: 10.1166/Jolpe.2006.005  0.41
2006 Ozdag RO, Beerel PA. An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates Ieee Transactions On Very Large Scale Integration Systems. 14: 975-985. DOI: 10.1109/Tvlsi.2006.884049  0.561
2006 Ferretti M, Beerel PA. High performance asynchronous design using single-track full-buffer standard cells Ieee Journal of Solid-State Circuits. 41: 1444-1454. DOI: 10.1109/Jssc.2006.874308  0.696
2005 Tugsinavisut S, Hong Y, Kim D, Kim K, Beerel PA. Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication Ieee Transactions On Very Large Scale Integration Systems. 13: 448-461. DOI: 10.1109/Tvlsi.2004.842908  0.532
2003 Moon JS, Athas WC, Soli SD, Draper JT, Beerel. PA. Voltage-Pulse Driven Harmonic Resonant Rail Drivers for Low-Power Applications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 762-777. DOI: 10.1109/Tvlsi.2003.814323  0.518
2002 Beerel PA, Xie A. Performance Analysis of Asynchronous Circuits Using Markov Chains Lecture Notes in Computer Science. 313-344. DOI: 10.1007/3-540-36190-1_9  0.572
2001 Beerel PA, Chugg KM. A low latency SISO with application to broadband turbo decoding Ieee Journal On Selected Areas in Communications. 19: 860-870. DOI: 10.1109/49.924870  0.368
2001 Stevens KS, Rotem S, Ginosar R, Beerel P, Myers CJ, Yun KY, Koi R, Dike C, Roncken M. An asynchronous instruction length decoder Ieee Journal of Solid-State Circuits. 36: 217-228. DOI: 10.1109/4.902762  0.507
2000 Hong Y, Beerel PA, Burch JR, McMillan KL. Sibling-substitution-based BDD minimization using don't cares Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 44-55. DOI: 10.1109/43.822619  0.355
1999 Chou W, Beerel PA, Yun KY. Average-case technology mapping of asynchronous burst-mode circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1418-1434. DOI: 10.1109/43.790619  0.467
1999 Xie A, Beerel PA. Accelerating Markovian analysis of asynchronous systems using state compression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 869-888. DOI: 10.1109/43.771173  0.369
1999 KyeounsooKim, Beerel PA. MSB-controlled inversion coding for a low-power matrix transposer Electronics Letters. 35: 1434-1435. DOI: 10.1049/El:19990910  0.374
1999 Yenigun H, Levin V, Peled D, Beerel PA. Hazard-freedom checking in speed-independent systems Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1703: 317-321. DOI: 10.1007/3-540-48153-2_24  0.435
1998 Yun KY, Beerel PA, Vakilotojar V, Dooply AE, Arceo J. The design and verification of a high-performance low-control-overhead asynchronous differential equation solver Ieee Transactions On Very Large Scale Integration Systems. 6: 643-655. DOI: 10.1109/92.736138  0.666
1998 Xie A, Beerel PA. Efficient state classification of finite-state Markov chains Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 1334-1339. DOI: 10.1109/43.736573  0.316
1998 Beerel P, Myers C, Meng T. Covering conditions and algorithms for the synthesis of speed-independent circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 205-219. DOI: 10.1109/43.700719  0.467
1997 Vakilotojar V, Beerel PA. RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking Integration. 24: 19-35. DOI: 10.1016/S0167-9260(97)00023-0  0.652
1996 Beerel PA, Hsieh CT, Wadekar S. Estimation of energy consumption in speed-independent control circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 672-680. DOI: 10.1109/43.503936  0.459
1992 Beerel PA, Meng TH. Semi-modularity and testability of speed-independent circuits Integration. 13: 301-322. DOI: 10.1016/0167-9260(92)90033-U  0.494
Show low-probability matches.