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Naran Sirisantana, Ph.D. - Publications

Affiliations: 
2003 Purdue University, West Lafayette, IN, United States 
Area:
Electronics and Electrical Engineering
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9 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2005 Cao A, Sirisantana N, Koh CK, Roy K. Synthesis of skewed logic circuits Acm Transactions On Design Automation of Electronic Systems. 10: 205-228. DOI: 10.1145/1059876.1059878  0.643
2004 Sirisantana N, Paul BC, Roy K. Enhancing yield at the end of the technology roadmap Ieee Design and Test of Computers. 21: 563-571. DOI: 10.1109/Mdt.2004.86  0.501
2004 Sirisantana N, Roy K. Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses Ieee Design and Test of Computers. 21: 56-63. DOI: 10.1109/Mdt.2004.1261850  0.542
2003 Sirisantana N, Roy K. A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies European Solid-State Circuits Conference. 181-184. DOI: 10.1109/ESSCIRC.2003.1257102  0.649
2003 Sirisantana N, Roy K. Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies Proceedings -Design, Automation and Test in Europe, Date. 1160-1161. DOI: 10.1109/DATE.2003.1253781  0.645
2003 Cao A, Sirisantana N, Koh CK, Roy K. Integer linear programming-based synthesis of skewed logic circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 820-823. DOI: 10.1109/ASPDAC.2003.1195131  0.617
2002 Solomatnikov A, Somasekhar D, Sirisantana N, Roy K. Skewed CMOS: Noise-tolerant high-performance low-power static circuit family Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 469-476. DOI: 10.1109/Tvlsi.2002.800519  0.656
2002 Cao A, Sirisantana N, Koh CK, Roy K. Synthesis of selectively clocked skewed logic circuits Proceedings - International Symposium On Quality Electronic Design, Isqed. 2002: 229-234. DOI: 10.1109/ISQED.2002.996737  0.661
2001 Sirisantana N, Cao A, Davidson S, Koh CK, Roy K. Selectively clocked skewed logic (SCSl): A robust low-power logic style for high-performance applications Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 267-270.  0.695
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