Xiaoliang Bai, Ph.D. - Publications
Affiliations: | 2003 | University of California, San Diego, La Jolla, CA |
Area:
Electronics and Electrical EngineeringYear | Citation | Score | |||
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2007 | Zhao C, Bai X, Dey S. Evaluating Transient Error Effects in Digital Nanometer Circuits Ieee Transactions On Reliability. 56: 381-391. DOI: 10.1109/Tr.2007.903288 | 0.52 | |||
2005 | Zhao C, Dey S, Bai X. Soft-spot analysis: targeting compound noise effects in nanometer circuits Ieee Design & Test of Computers. 22: 362-375. DOI: 10.1109/Mdt.2005.95 | 0.538 | |||
2004 | Bai X, Dey S. High-level crosstalk defect Simulation methodology for system-on-chip interconnects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1355-1361. DOI: 10.1109/Tcad.2004.833612 | 0.492 | |||
2004 | Bai X, Chandra R, Dey S, Srinivas PV. Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1256-1263. DOI: 10.1109/Tcad.2004.831568 | 0.526 | |||
2002 | Chen L, Bai X, Dey S. Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores Journal of Electronic Testing. 18: 529-538. DOI: 10.1023/A:1016562011549 | 0.456 | |||
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