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Radu M. Secareanu, Ph.D. - Publications

Affiliations: 
2000 Electrical and Computer Engineering University of Rochester, Rochester, NY 
 2008- Freescale Semiconductor 
Area:
Electronics and Electrical Engineering
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29 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Stockinger M, Secareanu R. Unexpected Latch-Up Through CMOS Triple-Well Structures Ieee Transactions On Device and Materials Reliability. 15: 272-279. DOI: 10.1109/Tdmr.2015.2466532  0.347
2013 Kose S, Friedman EG, Secareanu RM, Hartin O. Current profile of a microcontroller to determine electromagnetic emissions Proceedings - Ieee International Symposium On Circuits and Systems. 2650-2653. DOI: 10.1109/ISCAS.2013.6572423  0.564
2010 Jakushokas R, Salman E, Friedman EG, Secareanu RM, Hartin OL, Recker CL. Compact substrate models for efficient noise coupling and signal isolation analysis Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2346-2349. DOI: 10.1109/ISCAS.2010.5537192  0.743
2009 Salman E, Jakushokas R, Friedman EG, Secareanu RM, Hartin OL. Contact merging algorithm for efficient substrate noise analysis in large scale circuits Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 9-14. DOI: 10.1145/1531542.1531550  0.791
2009 Salman E, Friedman EG, Secareanu RM, Hartin OL. Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1559-1564. DOI: 10.1109/Tvlsi.2008.2005195  0.751
2009 Salman E, Jakushokas R, Friedman EG, Secareanu RM, Hartin OL. Methodology for efficient substrate noise analysis in large-scale mixed-signal circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1405-1418. DOI: 10.1109/Tvlsi.2008.2003518  0.79
2009 Salman E, Friedman EG, Secareanu RM, Hartin OL. Worst case power/ground noise estimation using an equivalent transition time for resonance Ieee Transactions On Circuits and Systems I: Regular Papers. 56: 997-1004. DOI: 10.1109/Tcsi.2009.2016614  0.735
2008 Popovich M, Friedman EG, Secareanu RM, Hartin OL. Efficient distributed on-chip decoupling capacitors for nanoscale ICs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 1717-1721. DOI: 10.1109/Tvlsi.2008.2001735  0.678
2008 Salman E, Friedman EG, Secareanu RM, Hartin OL. Dominant substrate noise coupling mechanism for multiple switching gates Proceedings of the 9th International Symposium On Quality Electronic Design, Isqed 2008. 261-266. DOI: 10.1109/ISQED.2008.4479736  0.772
2008 Salman E, Friedman EG, Secareanu RM, Hartin OL. Equivalent rise time for resonance in power/ground noise estimation Proceedings - Ieee International Symposium On Circuits and Systems. 2422-2425. DOI: 10.1109/ISCAS.2008.4541944  0.739
2008 Salman E, Jakushokas R, Friedman EG, Secareanu RM, Hartin OL. Input port reduction for efficient substrate extraction in large scale IC's Proceedings - Ieee International Symposium On Circuits and Systems. 376-379. DOI: 10.1109/ISCAS.2008.4541433  0.773
2007 Secareanu RM, Marshall A. Guest editorial special section on system-on-chip integration: Challenges and implications Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1065-1066. DOI: 10.1109/Tvlsi.2007.903909  0.329
2007 Salman E, Friedman EG, Secareanu RM. Substrate and ground noise interactions in mixed-signal circuits 2006 Ieee International Systems-On-Chip Conference, Soc. 293-296. DOI: 10.1109/SOCC.2006.283901  0.778
2007 Popovich M, Friedman EG, Secareanu RM, Hartin OL. Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 811-816. DOI: 10.1109/ICCAD.2007.4397365  0.589
2007 Salman E, Friedman EG, Secareanu RM, Hartin OL. Substrate noise reduction based on noise aware cell design Proceedings - Ieee International Symposium On Circuits and Systems. 3227-3230.  0.707
2006 Popovich M, Friedman EG, Sotman M, Kolodny A, Secareanu RM. Maximum effective distance of on-chip decoupling capacitors in power distribution grids Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 173-179.  0.373
2005 Secareanu RM, Banerjee SK, Hartin O, Fernandez V, Friedman EG. Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment Proceedings - Ieee International Symposium On Circuits and Systems. 612-615. DOI: 10.1109/ISCAS.2005.1464662  0.652
2004 Secareanu RM, Warner S, Seabridge S, Burke C, Becerra J, Watrobski TE, Morton C, Staub W, Tellier T, Kourtev IS, Friedman EG. Substrate Coupling in Digital Circuits in Mixed-Signal Smart-Power Systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 67-78. DOI: 10.1109/Tvlsi.2003.820526  0.802
2004 Secareanu RM, Peterson B. An adaptive circuits concept to address mismatch in analog circuits Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.334
2004 Secareanu RM, Li Q, Bharatan S, Kyono C, Thoma R, Miller M, Hartin O. Signal integrity implications of inductor-to-circuit proximity Proceedings - Ieee International Soc Conference. 69-72.  0.363
2002 Secareanu RM, Hartman D. A low-voltage low-noise CMOS digital family Proceedings of the Annual Ieee International Asic Conference and Exhibit. 2002: 198-202. DOI: 10.1109/ASIC.2002.1158056  0.404
2002 Secareanu RM, Peterson B, Hartman D. A low-voltage low-noise digital buffer system Proceedings - Ieee International Symposium On Circuits and Systems. 4.  0.428
2002 Kursun V, Secareanu RM, Friedman EG. CMOS voltage interface circuit for low power systems Proceedings - Ieee International Symposium On Circuits and Systems. 3.  0.705
2001 Secareanu RM, Friedman EG. Applying analog techniques in digital CMOS buffers to improve speed and noise immunity Analog Integrated Circuits and Signal Processing. 27: 275-279. DOI: 10.1023/A:1011257908593  0.693
2001 Secareanu RM, Warner S, Seabridge S, Burke C, Watrobski TE, Morton C, Staub W, Tellier T, Friedman EG. Placement of substrate contacts to minimize substrate noise in mixed-signal integrated circuits Analog Integrated Circuits and Signal Processing. 28: 253-264. DOI: 10.1023/A:1011204026940  0.703
2001 Secareanu RM, Albonesi D, Friedman EG. A dynamic reconfigurable clock generator Proceedings of the Annual Ieee International Asic Conference and Exhibit. 330-333.  0.487
2001 Secareanu RM, Warner S, Seabridge S, Burke C, Watrobski TE, Morton C, Staub W, Tellier T, Friedman EG. A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 1: 181-184.  0.51
2000 Secareanu RM, Warner S, Seabridge S, Burke C, Watrobski TE, Morton C, Staub W, Tellier T, Friedman EG. Placement of substrate contacts to alleviate substrate noise in epi and non-epi technologies Midwest Symposium On Circuits and Systems. 3: 1314-1319.  0.466
2000 Secareanu RM, Friedman EG. Low power digital CMOS buffer systems for driving highly capacitive interconnect lines Midwest Symposium On Circuits and Systems. 1: 362-365.  0.584
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