| Year |
Citation |
Score |
| 2019 |
Shi C, Rani A, Thomson B, Debnath R, Motayed A, Ioannou DE, Li Q. High-performance room-temperature TiO2-functionalized GaN nanowire gas sensors Applied Physics Letters. 115: 121602. DOI: 10.1063/1.5116677 |
0.389 |
|
| 2018 |
Georgiou V, Veksler D, Campbell JP, Shrestha PR, Ryan JT, Ioannou DE, Cheung KP. Ferroelectricity in Polar Polymer-based FETs: A Hysteresis Analysis. Advanced Functional Materials. 28. PMID 31080381 DOI: 10.1002/Adfm.201705250 |
0.329 |
|
| 2017 |
Gu K, Yu S, Eshun K, Yuan H, Ye H, Tang J, Ioannou DE, Xiao C, Wang H, Li Q. Two-dimensional hybrid layered materials: Strain Engineering on the Band Structure of MoS2/WSe2 hetero-multilayers. Nanotechnology. PMID 28627501 DOI: 10.1088/1361-6528/Aa7A34 |
0.303 |
|
| 2017 |
Georgiou V, Veksler D, Ryan JT, Campbell JP, Shrestha PR, Ioannou DE, Cheung KP. Highly Efficient Rapid Annealing of Thin Polar Polymer Film Ferroelectric Devices at Sub-Glass Transition Temperature Advanced Functional Materials. 28: 1704165. DOI: 10.1002/Adfm.201704165 |
0.308 |
|
| 2016 |
Chbili Z, Cheung KP, Campbell JP, Chbili J, Lahbabi M, Ioannou DE, Matocha K. Time dependent dielectric breakdown in high quality SiC MOS capacitors Materials Science Forum. 858: 615-618. DOI: 10.4028/Www.Scientific.Net/Msf.858.615 |
0.374 |
|
| 2016 |
Chbili Z, Matsuda A, Chbili J, Ryan JT, Campbell JP, Lahbabi M, Ioannou DE, Cheung KP. Modeling early breakdown failures of gate oxide in SiC power MOSFETs Ieee Transactions On Electron Devices. 63: 3605-3613. DOI: 10.1109/Ted.2016.2586483 |
0.357 |
|
| 2015 |
Yuan H, Cheng G, You L, Li H, Zhu H, Li W, Kopanski JJ, Obeng YS, Hight Walker AR, Gundlach DJ, Richter CA, Ioannou DE, Li Q. Influence of metal-MoS2 interface on MoS2 transistor performance: comparison of Ag and Ti contacts. Acs Applied Materials & Interfaces. 7: 1180-7. PMID 25514512 DOI: 10.1021/Am506921Y |
0.308 |
|
| 2015 |
Badwan AZ, Chbili Z, Li Q, Ioannou DE. SOI FED-SRAM Cell: Structure and Operation Ieee Transactions On Electron Devices. 62: 2865-2870. DOI: 10.1109/Ted.2015.2450693 |
0.362 |
|
| 2015 |
Badwan AZ, Li Q, Ioannou DE. On the Nature of the Memory Mechanism of Gated-Thyristor Dynamic-RAM Cells Ieee Journal of the Electron Devices Society. 3: 468-471. DOI: 10.1109/Jeds.2015.2480377 |
0.344 |
|
| 2014 |
Li Q, Xiong HD, Liang X, Zhu X, Gu D, Ioannou DE, Baumgart H, Richter CA. Self-assembled nanowire array capacitors: capacitance and interface state profile. Nanotechnology. 25: 135201. PMID 24584362 DOI: 10.1088/0957-4484/25/13/135201 |
0.581 |
|
| 2014 |
Chbili Z, Shreshta PR, Campbell JP, Suehle JS, Ioannou DE, Cheung KP. Unexpected effect of thermal storage observed on SiC power DMOSFET Materials Science Forum. 778: 529-532. DOI: 10.4028/Www.Scientific.Net/Msf.778-780.529 |
0.409 |
|
| 2014 |
Yuan H, Badwan A, Richter CA, Zhu H, Kirillov O, Ioannou DE, Li Q. Gate assisted Kelvin test structure to measure the electron and hole flows at the same nanowire contacts Applied Physics Letters. 105. DOI: 10.1063/1.4897008 |
0.423 |
|
| 2013 |
Zhu H, Yuan H, Li H, Richter CA, Kirillov O, Ioannou DE, Li Q. Design and fabrication of Ta2O5 stacks for discrete multibit memory application Ieee Transactions On Nanotechnology. 12: 1151-1157. DOI: 10.1109/Tnano.2013.2281817 |
0.362 |
|
| 2013 |
Badwan AZ, Chbili Z, Yang Y, Salman AA, Li Q, Ioannou DE. SOI field-effect diode DRAM cell: Design and operation Ieee Electron Device Letters. 34: 1002-1004. DOI: 10.1109/Led.2013.2265552 |
0.707 |
|
| 2013 |
Zhu H, Hacker CA, Pookpanratana SJ, Richter CA, Yuan H, Li H, Kirillov O, Ioannou DE, Li Q. Non-volatile memory with self-assembled ferrocene charge trapping layer Applied Physics Letters. 103. DOI: 10.1063/1.4817009 |
0.398 |
|
| 2013 |
Zhu H, Richter CA, Zhao E, Bonevich JE, Kimes WA, Jang HJ, Yuan H, Li H, Arab A, Kirillov O, Maslar JE, Ioannou DE, Li Q. Topological insulator Bi2Se3 nanowire high performance field-effect transistors Scientific Reports. 3. DOI: 10.1038/Srep01757 |
0.452 |
|
| 2012 |
Zhu H, Li Q, Yuan H, Baumgart H, Ioannou DE, Richter CA. Self-aligned multi-channel silicon nanowire field-effect transistors Solid-State Electronics. 78: 92-96. DOI: 10.1016/J.Sse.2012.05.058 |
0.488 |
|
| 2011 |
Zhu X, Li Q, Ioannou DE, Gu D, Bonevich JE, Baumgart H, Suehle JS, Richter CA. Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells. Nanotechnology. 22: 254020. PMID 21572210 DOI: 10.1088/0957-4484/22/25/254020 |
0.565 |
|
| 2011 |
Yang Y, Gauthier RJ, Chatty K, Li J, Mishra R, Mitra S, Ioannou DE. Degradation of high-κ/metal gate nMOSFETs under ESD-like stress in a 32-nm technology Ieee Transactions On Device and Materials Reliability. 11: 118-125. DOI: 10.1109/Tdmr.2010.2098407 |
0.594 |
|
| 2010 |
Vu VA, Ioannou DE, Kamocsai R, Hyland SL, Pomerene A, Carothers D. PIN germanium photodetector fabrication issues and manufacturability Ieee Transactions On Semiconductor Manufacturing. 23: 411-418. DOI: 10.1109/Tsm.2010.2050080 |
0.345 |
|
| 2010 |
Mishra R, Ioannou DE, Mitra S, Gauthier R, Seguin C, Halbach R. ESD performance of 65 nm partially depleted n and p channel SOI MOSFETs Solid-State Electronics. 54: 357-361. DOI: 10.1016/J.Sse.2009.12.030 |
0.659 |
|
| 2009 |
Li Q, Zhu X, Yang Y, Ioannou DE, Xiong HD, Kwon DW, Suehle JS, Richter CA. The large-scale integration of high-performance silicon nanowire field effect transistors. Nanotechnology. 20: 415202. PMID 19755723 DOI: 10.1088/0957-4484/20/41/415202 |
0.636 |
|
| 2009 |
Zhu X, Gu D, Li Q, Ioannou DE, Baumgart H, Suehle JS, Richter CA. Silicon nanowire NVM with high-k gate dielectric stack Microelectronic Engineering. 86: 1957-1960. DOI: 10.1016/J.Mee.2009.03.095 |
0.567 |
|
| 2008 |
Richter CA, Xiong HD, Zhu X, Wang W, Stanford VM, Hong WK, Lee T, Ioannou DE, Li Q. Metrology for the electrical characterization of semiconductor nanowires Ieee Transactions On Electron Devices. 55: 3086-3095. DOI: 10.1109/Ted.2008.2005394 |
0.594 |
|
| 2008 |
Mishra R, Ioannou DE, Mitra S, Gauthier R. Effect of floating-body and stress bias on NBTI and HCI on 65-nm SOI pMOSFETs Ieee Electron Device Letters. 29: 262-264. DOI: 10.1109/Led.2007.915382 |
0.409 |
|
| 2008 |
Yang Y, Salman AA, Ioannou DE, Beebe SG. Design and optimization of the SOI field effect diode (FED) for ESD protection Solid-State Electronics. 52: 1482-1485. DOI: 10.1016/J.Sse.2008.06.033 |
0.746 |
|
| 2008 |
Zhu X, Yang Y, Li Q, Ioannou DE, Suehle JS, Richter CA. Silicon nanowire NVM cell using high-k dielectric charge storage layer Microelectronic Engineering. 85: 2403-2405. DOI: 10.1016/J.Mee.2008.09.013 |
0.593 |
|
| 2007 |
Verrelli E, Tsoukalas D, Giannakopoulos K, Ioannou D. Deposition Of Uniform Size Metallic Nanoparticles For Use In Non Volatile Memories Mrs Proceedings. 997. DOI: 10.1557/Proc-0997-I03-08 |
0.341 |
|
| 2007 |
Li Q, Zhu X, Xiong HD, Koo SM, Ioannou DE, Kopanski JJ, Suehle JS, Richter CA. Silicon nanowire on oxide/nitride/oxide for memory application Nanotechnology. 18. DOI: 10.1088/0957-4484/18/23/235204 |
0.604 |
|
| 2007 |
Ioannou DP, Ioannou DE. Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors Solid-State Electronics. 51: 268-277. DOI: 10.1016/J.Sse.2007.01.004 |
0.466 |
|
| 2007 |
Verrelli E, Tsoukalas D, Giannakopoulos K, Kouvatsos D, Normand P, Ioannou DE. Nickel nanoparticle deposition at room temperature for memory applications Microelectronic Engineering. 84: 1994-1997. DOI: 10.1016/J.Mee.2007.04.078 |
0.345 |
|
| 2007 |
Mishra R, Mitra S, Gauthier R, Ioannou DE, Seguin C, Halbach R. Concurrent HCI-NBTI: worst case degradation condition for 65 nm p-channel SOI MOSFETs Microelectronic Engineering. 84: 2085-2088. DOI: 10.1016/J.Mee.2007.04.016 |
0.465 |
|
| 2004 |
Ioannou DP, Ioannou DE. Beta engineering and circuit styles for SEU hardening PD-SOI SRAM cells Solid-State Electronics. 48: 1947-1951. DOI: 10.1016/J.Sse.2004.05.040 |
0.414 |
|
| 2004 |
Mitra S, Salman A, Ioannou DP, Tretz C, Ioannou DE. Double gate (DG)-SOI ratioed logic with symmetric DG load - A novel approach for sub 50 nm low-voltage/low-power circuit design Solid-State Electronics. 48: 1727-1732. DOI: 10.1016/J.Sse.2004.05.006 |
0.72 |
|
| 2003 |
Salman AA, Gauthier R, Putnam C, Riess P, Muhammad M, Woo M, Ioannou DE. ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-μm CMOS technology Ieee Transactions On Device and Materials Reliability. 3: 79-84. DOI: 10.1109/Tdmr.2003.815275 |
0.721 |
|
| 2002 |
Mittereder JA, Roussos JA, Anderson WT, Ioannou DE. Quantitative measurement of channel temperature of GaAs devices for reliable life-time prediction Ieee Transactions On Reliability. 51: 482-485. DOI: 10.1109/Tr.2002.804487 |
0.743 |
|
| 2002 |
Salman A, Gauthier R, Stadler W, Esmark K, Muhammad M, Putnam C, Ioannou DE. NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology Ieee Transactions On Device and Materials Reliability. 2: 2-8. DOI: 10.1109/Tdmr.2002.1014666 |
0.753 |
|
| 2002 |
Pretet J, Subba N, Ioannou D, Cristoloveanu S, Maszara W, Raynaud C. Reduced floating body effects in narrow channel SOI MOSFETs Ieee Electron Device Letters. 23: 55-57. DOI: 10.1109/55.974811 |
0.402 |
|
| 2002 |
Pretet J, Ioannou D, Subba N, Cristoloveanu S, Maszara W, Raynaud C. Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs Solid-State Electronics. 46: 1699-1707. DOI: 10.1016/S0038-1101(02)00147-8 |
0.439 |
|
| 2002 |
Buot FA, Mittereder JA, Anderson WT, Ioannou DE. Transient thermal simulations of a three-dimensional unit cell in power control systems and high-power microwave devices Solid-State Electronics. 46: 123-131. DOI: 10.1016/S0038-1101(01)00204-0 |
0.743 |
|
| 2001 |
Zhao X, Salman A, Ioannou DE, Jenkins WC, Hughes HL. “Gated-diode” configuration in SOI MOSFET’s: A sensitive tool for evaluating the quality and reliability of the buried Si/SiO2 interface Characterization and Metrology For Ulsi Technology. 550: 226-230. DOI: 10.1063/1.1354402 |
0.761 |
|
| 2001 |
Pretet J, Subba N, Ioannou D, Cristoloveanu S, Maszara W, Raynaud C. Channel-width dependence of floating body effects in STI- and LOCOS-isolated MOSFETS Microelectronic Engineering. 59: 483-488. DOI: 10.1016/S0167-9317(01)00662-1 |
0.442 |
|
| 2001 |
Anderson WT, Roussos JA, Mittereder JA, Ioannou DE, Moglestue C. Pseudomorphic high electron mobility transistor monolithic microwave integrated circuits reliability study Microelectronics Reliability. 41: 1109-1113. DOI: 10.1016/S0026-2714(01)00082-8 |
0.719 |
|
| 1998 |
Ioannou DE, Duan FL, Sinha SP, Zaleski A. Opposite-channel-based injection of hot-carriers in SOI MOSFET's: physics and applications Ieee Transactions On Electron Devices. 45: 1147-1154. DOI: 10.1109/16.669576 |
0.432 |
|
| 1997 |
Duan FL, Sinha SP, Ioannou DE, Brady FT. LDD design tradeoffs for single transistor latch-up and hot carrier degradation control in accumulation mode FD SOI mosfet's Ieee Transactions On Electron Devices. 44: 972-977. DOI: 10.1109/16.585553 |
0.423 |
|
| 1996 |
Sinha SP, Zaleski A, Ioannou DE, Campisi GJ, Hughes HL. Hot hole induced interface state generation and annihilation in SOI MOSFET's Ieee Electron Device Letters. 17: 121-123. DOI: 10.1109/55.485187 |
0.341 |
|
| 1995 |
Zaleski A, Sinha SP, Ioannou DE, Campisi GJ, Hughes HL. Opposite-Channel-Based Charge Injection in SOI MOSFET's Under Hot Carrier Stress Ieee Transactions On Electron Devices. 42: 1697-1700. DOI: 10.1109/16.405288 |
0.381 |
|
| 1995 |
Sinha SP, Zaleski A, Ioannou DE, Campisi GJ, Hughes HL. In-depth analysis of opposite channel based charge injection in SOI MOSFETs and related defect creation and annihilation Microelectronic Engineering. 28: 383-386. DOI: 10.1016/0167-9317(95)00081-I |
0.389 |
|
| 1994 |
Sinha SP, Zaleski A, Ioannou DE. Investigation of Carrier Generation in Fully Depleted Enhancement and Accumulation Mode SOI MOSFET’s Ieee Transactions On Electron Devices. 41: 2413-2416. DOI: 10.1109/16.337457 |
0.419 |
|
| 1993 |
Zaleski A, Campisi GJ, Ioannou DE, Hughes HL. Successive Charging/Discharging of Gate Oxides in SOI MOSFET’s by Sequential Hot-Electron Stressing of Front/Back Channel Ieee Electron Device Letters. 14: 435-437. DOI: 10.1109/55.244715 |
0.405 |
|
| 1993 |
Zaleski A, Ioannou DE, Campisi GJ, Hughes HL. Mechanisms of hot-carrier induced degradation of SOI (SIMOX) MOSFET's Microelectronic Engineering. 22: 403-406. DOI: 10.1016/0167-9317(93)90198-E |
0.411 |
|
| 1992 |
Cristoloveanu S, Gulwadi SM, Ioannou DE, Campisi GJ, Hughes HL. Hot-electron-induced degradation of front and back channels in partially and fully depleted SIMOX MOSFETs Ieee Electron Device Letters. 13: 603-605. DOI: 10.1109/55.192858 |
0.405 |
|
| 1991 |
Ioannou DE, Zhong X, Mazhari B, Campisi GJ, Hughes HL. Interface characterization of fully depleted SOI MOSFETs by the dynamic transconductance technique Ieee Electron Device Letters. 12: 430-432. DOI: 10.1109/55.119155 |
0.362 |
|
| 1991 |
Mazhari B, Cristoloveanu S, Ioannou DE, Caviglia AL. Properties of ultra-thin wafer-bonded silicon-on-insulator MOSFET's Ieee Transactions On Electron Devices. 38: 1289-1295. DOI: 10.1109/16.81619 |
0.425 |
|
| 1991 |
Ioannou DE, Cristoloveanu S, Potamianos CN, Zhong X, McLarty PK, Hughes HL. Optimization of SIMOX for VLSI by electrical characterization Ieee Transactions On Electron Devices. 38: 463-468. DOI: 10.1109/16.75154 |
0.359 |
|
| 1990 |
Ioannou DE, Cristoloveanu S, Mukherjee M, Mazhari B. Characterization of carrier generation in enhancement-mode SOI MOSFET's Ieee Electron Device Letters. 11: 409-411. DOI: 10.1109/55.62972 |
0.425 |
|
| 1990 |
McLarty PK, Ioannou DE. DLTS analysis of carrier generation transients in thin SOI MOSFETs Ieee Transactions On Electron Devices. 37: 262-266. DOI: 10.1109/16.43823 |
0.351 |
|
| 1990 |
Frey J, Ioannou DE. Chapter 1 Materials and Devices for High-Speed and Optoelectronic Applications Semiconductors and Semimetals. 28: 1-40. DOI: 10.1016/S0080-8784(08)62783-0 |
0.399 |
|
| 1990 |
Cristoloveanu S, Ioannou DE. Adjustable confinement of the electron gas in dual-gate silicon-on-insulator mosfet's Superlattices and Microstructures. 8: 131-135. DOI: 10.1016/0749-6036(90)90290-N |
0.349 |
|
| 1990 |
McLarty PK, Ioannou DE, Hughes HL. The effect of post-implantation annealing temperature on the deep states present in SIMOX MOSFET's as observed using enhancement mode current DLTS Journal of Electronic Materials. 19: 449-452. DOI: 10.1007/Bf02658005 |
0.326 |
|
| 1990 |
Ioannou DE. Reliability of Short Channel Silicon and SOI VLSI Devices and Circuits Nato Asi Series. Series E, Applied Sciences. 175: 507-516. DOI: 10.1007/978-94-009-2482-6_30 |
0.472 |
|
| 1988 |
McLarty PK, Ioannou DE, Hughes HL. Deep states in silicon‐on‐insulator substrates prepared by oxygen implantation using current deep level transient spectroscopy Applied Physics Letters. 53: 871-873. DOI: 10.1063/1.100099 |
0.316 |
|
| 1987 |
Ioannou DE, Papanicolaou NA, Nordquist PE. The effect of heat treatment on Au Schottky contacts on β-SiC Ieee Transactions On Electron Devices. 34: 1694-1699. DOI: 10.1109/T-Ed.1987.23139 |
0.363 |
|
| 1987 |
Ioannou DE, Panagiotopoulos D. A fine-line-spot-position (FLSP) sensitive photodetector Ieee Transactions On Electron Devices. 34: 778-781. DOI: 10.1109/T-Ed.1987.22996 |
0.313 |
|
| 1982 |
Hemment PLF, Maydell-Ondrusz E, Stephens KG, Butcher J, Ioannou D, Alderman J. FORMATION OF BURIED INSULATING LAYERS IN SILICON BY THE IMPLANTATION OF HIGH DOSES OF OXYGEN Nuclear Instruments and Methods in Physics Research. 209: 157-164. DOI: 10.1016/0167-5087(83)90794-9 |
0.312 |
|
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