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Igor L. Markov, Ph.D. - Publications

Affiliations: 
2001 University of California, Los Angeles, Los Angeles, CA 
Area:
Computer Science, Electronics and Electrical Engineering, Mathematics
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Year Citation  Score
2015 Plaza SM, Markov IL. Solving the third-shift problem in IC piracy with test-aware logic locking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 961-971. DOI: 10.1109/Tcad.2015.2404876  0.306
2015 Garcia HJ, Markov IL. Simulation of quantum circuits via stabilizer frames Ieee Transactions On Computers. 64: 2323-2336. DOI: 10.1109/Tc.2014.2360532  0.321
2014 Markov IL. Limits on fundamental limits to computation. Nature. 512: 147-54. PMID 25119233 DOI: 10.1038/Nature13570  0.39
2013 Nadakuditi RR, Markov IL. On bottleneck analysis in stochastic stream processing Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2491477.2491478  0.359
2013 Kim MC, Lee DJ, Markov IL. SimPL: An algorithm for placing VLSI circuits Communications of the Acm. 56: 105-113. DOI: 10.1145/2461256.2461279  0.419
2013 Saeedi M, Markov IL. Synthesis and optimization of reversible circuits-a survey Acm Computing Surveys. 45. DOI: 10.1145/2431211.2431220  0.389
2013 Kahng AB, Kang S, Lee H, Markov IL, Thapar P. High-performance gate sizing with a signoff timer Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 450-457. DOI: 10.1109/ICCAD.2013.6691156  0.518
2013 Markov IL, Saeedi M. Faster quantum number factoring via circuit synthesis Physical Review a - Atomic, Molecular, and Optical Physics. 87. DOI: 10.1103/Physreva.87.012310  0.373
2013 Papa DA, Markov IL. Co-optimization of latches and clock networks Lecture Notes in Electrical Engineering. 166: 133-148. DOI: 10.1007/978-1-4614-1356-1-9  0.318
2012 Lee DJ, Markov IL. Obstacle-aware clock-tree shaping during placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 205-216. DOI: 10.1109/Tcad.2011.2173490  0.399
2012 Kim MC, Lee DJ, Markov IL. SimPL: An effective placement algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 50-60. DOI: 10.1109/Tcad.2011.2170567  0.391
2011 Papa D, Viswanathan N, Sze C, Li Z, Nam GJ, Alpert C, Markov IL. Physical synthesis with clock-network optimization for large systems on chips Ieee Micro. 31: 51-62. DOI: 10.1109/Mm.2011.41  0.402
2011 Markov IL. Getting Your Bits in Order Ieee Design & Test of Computers. 28: 98-101. DOI: 10.1109/Mdt.2011.86  0.363
2011 Kahng AB, Lienig J, Markov IL, Hu J. VLSI physical design: From graph partitioning to timing closure Vlsi Physical Design: From Graph Partitioning to Timing Closure. 1-310. DOI: 10.1007/978-90-481-9591-6  0.368
2010 Lee D, Markov IL. Contango: Integrated optimization of SoC clock networks Proceedings -Design, Automation and Test in Europe, Date. 1468-1473. DOI: 10.1155/2011/407507  0.388
2010 Chang KH, Bertacco V, Markov IL, Mishchenko A. Logic synthesis and circuit customization using extensive external don't-cares Acm Transactions On Design Automation of Electronic Systems. 15. DOI: 10.1145/1754405.1754411  0.331
2010 Markov I. Chips in 3D Ieee Design & Test of Computers. 27: 68-69. DOI: 10.1109/Mdt.2010.81  0.345
2010 Papa D, Moffitt MD, Alpert CJ, Markov IL. Speeding up physical synthesis with transactional timing analysis Ieee Design and Test of Computers. 27: 14-24. DOI: 10.1109/Mdt.2010.76  0.377
2010 Roy JA, Koushanfar F, Markov IL. Ending piracy of integrated circuits Computer. 43: 30-38. DOI: 10.1109/Mc.2010.284  0.327
2010 Katebi H, Markov IL. Large-scale boolean matching Proceedings -Design, Automation and Test in Europe, Date. 771-776.  0.305
2009 Krishnaswamy S, Plaza SM, Markov IL, Hayes JP. Signature-based SER analysis and design of logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 74-86. DOI: 10.1109/Tcad.2008.2009139  0.407
2009 Markov I. Book Review: A physical-design picture book Ieee Design & Test of Computers. 26: 100-101. DOI: 10.1109/Mdt.2009.68  0.379
2009 Roy JA, Ng AN, Aggarwal R, Ramachandran V, Markov IL. Solving modern mixed-size placement instances Integration, the Vlsi Journal. 42: 262-275. DOI: 10.1016/J.Vlsi.2008.09.003  0.423
2009 Aloul FA, Ramani A, Markov IL, Sakallah KA. Dynamic symmetry-breaking for Boolean satisfiability Annals of Mathematics and Artificial Intelligence. 57: 59-73. DOI: 10.1007/S10472-010-9173-2  0.348
2008 Roy JA, Papa DA, Markov IL. Fine control of local whitespace in placement Vlsi Design. 2008. DOI: 10.1155/2008/517919  0.434
2008 Markov I. What is post-silicon debug? Acm Sigda Newsletter. 38: 1-1. DOI: 10.1145/1862828.1862829  0.356
2008 Krishnaswamy S, Viamontes GF, Markov IL, Hayes JP. Probabilistic transfer matrices in symbolic reliability analysis of logic circuits Acm Transactions On Design Automation of Electronic Systems. 13. DOI: 10.1145/1297666.1297674  0.329
2008 Aloul FA, Ramani A, Markov IL, Sakallah KA. Symmetry breaking for pseudo-Boolean formulas Journal of Experimental Algorithmics. 12. DOI: 10.1145/1227161.1278375  0.333
2008 Markov IL, Shi Y. Simulating quantum computation by contracting tensor networks Siam Journal On Computing. 38: 963-981. DOI: 10.1137/050644756  0.303
2008 Roy JA, Markov IL. High-performance routing at the nanometer scale Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1066-1077. DOI: 10.1109/Tcad.2008.923255  0.389
2008 Plaza SM, Markov IL, Bertacco V. Optimizing non-monotonic interconnect using functional simulation and logic restructuring Proceedings of the International Symposium On Physical Design. 95-102. DOI: 10.1109/Tcad.2008.2006156  0.466
2008 Plaza SM, Markov IL, Bertacco VM. Optimizing nonmonotonic interconnect using functional simulation and logic restructuring Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2107-2119. DOI: 10.1109/TCAD.2008.2006156  0.359
2008 Papa DA, Luo T, Moffitt MD, Sze CN, Li Z, Nam GJ, Alpert CJ, Markov IL. RUMBLE: An incremental timing-driven physical-synthesis optimization algorithm Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 2156-2168. DOI: 10.1109/Tcad.2008.2006155  0.442
2008 Chang KH, Markov IL, Bertacco V. Fixing design errors with counterexamples and resynthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 184-188. DOI: 10.1109/Tcad.2007.907257  0.355
2008 Chang KH, Markov IL, Bertacco V. Automating postsilicon debugging and repair Computer. 41: 47-54. DOI: 10.1109/Mc.2008.212  0.351
2008 Chang Kh, Markov IL, Bertacco V. SafeResynth: A new technique for physical synthesis Integration, the Vlsi Journal. 41: 544-556. DOI: 10.1016/J.Vlsi.2008.01.004  0.402
2007 Chang KH, Markov IL, Bertacco V. Postplacement rewiring by exhaustive search for functional symmetries Acm Transactions On Design Automation of Electronic Systems. 12. DOI: 10.1145/1255456.1255469  0.413
2007 Roy JA, Markov IL. ECO-system: Embracing the change in placement Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 147-152. DOI: 10.1109/Tcad.2007.907271  0.403
2007 Roy JA, Markov IL. Seeing the forest and the trees: Steiner wirelength optimization in placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 632-644. DOI: 10.1109/Tcad.2006.888260  0.389
2007 Aloul FA, Ramani A, Sakallah KA, Markov IL. Solution and optimization of systems of pseudo-Boolean constraints Ieee Transactions On Computers. 56: 1415-1424. DOI: 10.1109/Tc.2007.1075  0.368
2007 Chang KH, Papa DA, Markov IL, Bertacco V. InVerS: An incremental verification system with circuit similarity metrics and error visualization Proceedings - Eighth International Symposium On Quality Electronic Design, Isqed 2007. 487-492. DOI: 10.1109/ISQED.2007.94  0.301
2007 Chang KH, Markov IL, Bertacco V. Safe delay optimization for physical synthesis Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 628-633. DOI: 10.1109/ASPDAC.2007.358056  0.308
2006 Ramani A, Markov IL, Sakallah KA, Aloul FA. Breaking instance-independent symmetries in exact graph coloring Journal of Artificial Intelligence Research. 26: 289-322. DOI: 10.1613/Jair.1637  0.376
2006 Moffitt MD, Ng AN, Markov IL, Pollack ME. Constraint-driven floorplan repair Proceedings - Design Automation Conference. 1103-1108. DOI: 10.1145/1391962.1391975  0.459
2006 Prasad AK, Shende VV, Markov IL, Hayes JP, Patel KN. Data structures and algorithms for simplifying reversible circuits Acm Journal On Emerging Technologies in Computing Systems. 2: 277-293. DOI: 10.1145/1216396.1216399  0.4
2006 Roy JA, Adya SN, Papa DA, Markov IL. Min-cut floorplacement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1313-1326. DOI: 10.1109/Tcad.2005.855969  0.452
2006 Shende VV, Bullock SS, Markov IL. Synthesis of quantum-logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1000-1010. DOI: 10.1109/Tcad.2005.855930  0.364
2006 Svore KM, Aho AV, Cross AW, Chuang I, Markov IL. A layered software architecture for quantum computing design tools Computer. 39: 74-83. DOI: 10.1109/Mc.2006.4  0.358
2006 Adya SN, Markov IL, Villarrubia PG. On whitespace and stability in physical synthesis Integration, the Vlsi Journal. 39: 340-362. DOI: 10.1016/J.Vlsi.2005.08.003  0.424
2006 Ng A, Markov IL, Aggarwal R, Ramachandran V. Solving hard instances of floorplacement Proceedings of the International Symposium On Physical Design. 2006: 170-177.  0.319
2005 Adya SN, Markov IL. Combinatorial techniques for mixed-size placement Acm Transactions On Design Automation of Electronic Systems. 10: 58-90. DOI: 10.1145/1044111.1044116  0.421
2005 Chang KH, Bertacco V, Markov IL. Simulation-based bug trace minimization with BMC-based refinement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 1042-1048. DOI: 10.1109/Tcad.2006.882511  0.385
2005 Motter DB, Roy JA, Markov IL. Resolution cannot polynomially simulate compressed-BFS Annals of Mathematics and Artificial Intelligence. 44: 121-156. DOI: 10.1007/S10472-004-8427-2  0.37
2004 Viamontes GF, Markov IL, Hayes JP. Graph-based simulation of quantum computation in the density matrix representation Proceedings of Spie - the International Society For Optical Engineering. 5436: 285-296. DOI: 10.1117/12.542767  0.328
2004 Patel KN, Markov IL. Error-correction and crosstalk avoidance in DSM busses Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1076-1080. DOI: 10.1109/Tvlsi.2004.827565  0.331
2004 Adya SN, Yildiz MC, Markov IL, Villarrubia PG, Parakh PN, Madden PH. Benchmarking for Large-Scale Placement and Beyond Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 472-487. DOI: 10.1109/Tcad.2004.825852  0.397
2004 Kahng AB, Markov IL, Reda S. Boosting: Min-cut placement with improved signal delay Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1098-1103. DOI: 10.1109/DATE.2004.1269039  0.478
2004 Shende VV, Bullock SS, Markov IL. Recognizing small-circuit structure in two-qubit operators Physical Review a - Atomic, Molecular, and Optical Physics. 70: 012310-1-012310-5. DOI: 10.1103/Physreva.70.012310  0.312
2004 Shende VV, Markov IL, Bullock SS. Minimal universal two-qubit controlled-NOT-based circuits Physical Review a - Atomic, Molecular, and Optical Physics. 69: 062321-1. DOI: 10.1103/Physreva.69.062321  0.329
2004 Darga PT, Liffiton MH, Sakallah KA, Markov IL. Exploiting structure in symmetry detection for CNF Proceedings - Design Automation Conference. 530-534.  0.301
2004 Adya SN, Chaturvedi S, Roy JA, Papa DA, Markov IL. Unification of partitioning, placement and floorplanning Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 550-557.  0.348
2003 Adya SN, Markov IL. Fixed-outline floorplanning: Enabling hierarchical design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1120-1135. DOI: 10.1109/Tvlsi.2003.817546  0.429
2003 Cao Y, Hu C, Huang X, Kahng AB, Markov IL, Oliver M, Stroobandt D, Sylvester D. Improved a priori interconnect predictions and technology extrapolation in the GTX system Ieee Transactions On Very Large Scale Integration Systems. 11: 3-14. DOI: 10.1109/Tvlsi.2002.808479  0.515
2003 Patel KN, Hayes JP, Markov IL. Fault testing for reversible circuits Proceedings of the Ieee Vlsi Test Symposium. 2003: 410-416. DOI: 10.1109/Tcad.2004.831576  0.335
2003 Caldwell AE, Kahng AB, Markov IL. Hierarchical whitespace allocation in top-down placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1550-1556. DOI: 10.1109/Tcad.2003.818375  0.592
2003 Aloul FA, Ramani A, Markov IL, Sakallah KA. Solving difficult instances of Boolean satisfiability in the presence of symmetry Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 1117-1137. DOI: 10.1109/Tcad.2003.816218  0.352
2003 Shende VV, Prasad AK, Markov IL, Hayes JP. Synthesis of reversible logic circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 710-722. DOI: 10.1109/Tcad.2003.811448  0.368
2003 Aloul FA, Sakallah KA, Markov IL. Efficient symmetry breaking for Boolean satisfiability Ijcai International Joint Conference On Artificial Intelligence. 271-276. DOI: 10.1109/Tc.2006.75  0.333
2003 Kahng AB, Markov IL. Impact of interoperability on CAD-IP reuse: an academic viewpoint Proceedings - International Symposium On Quality Electronic Design, Isqed. 2003: 208-213. DOI: 10.1109/ISQED.2003.1194733  0.397
2003 Viamontes GF, Markov IL, Hayes JP. Improving Gate-Level Simulation of Quantum Circuits Quantum Information Processing. 2: 347-380. DOI: 10.1023/B:Qinp.0000022725.70000.4A  0.304
2002 Caldwell AE, Markov IL, Kahng AB. Toward CAD-IP reuse: a web bookshelf of fundamental algorithms Ieee Design & Test of Computers. 19: 72-81. DOI: 10.1109/Mdt.2002.1003801  0.534
2002 Kahng AB, Mantik S, Markov IL. Min-max placement for large-scale timing optimization Proceedings of the International Symposium On Physical Design. 143-148.  0.746
2001 Baldick R, Kahng AB, Kennings A, Markov IL. Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 48: 947-956. DOI: 10.1109/81.940185  0.56
2001 Kahng AB, Lach J, Mangione-Smith WH, Mantik S, Markov IL, Potkonjak M, Tucker P, Wang H, Wolfe G. Constraint-based watermarking techniques for design IP protection Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1236-1252. DOI: 10.1109/43.952740  0.75
2000 Caldwell AE, Kahng AB, Markov IL. Iterative partitioning with varying node weights Vlsi Design. 11: 249-258. DOI: 10.1155/2000/15862  0.517
2000 Caldwell AE, Kahng AB, Markov IL. Improved algorithms for hypergraph bipartitioning Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 661-666. DOI: 10.1145/368434.368864  0.453
2000 Caldwell AE, Kahng AB, Markov IL. Design and implementation of move-based heuristics for VLSI hypergraph partitioning Acm Journal of Experimental Algorithmics. 5: 5. DOI: 10.1145/351827.384247  0.596
2000 Caldwell AE, Kahng AB, Markov IL. Optimal partitioners and endcase placers for standardcell layout Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 13041313. DOI: 10.1109/43.892854  0.594
2000 Caldwell AE, Kahng AB, Markov IL. Optimal partitioners and end-case placers for standard-cell layout Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1304-1313. DOI: 10.1109/43.892854  0.429
2000 Alpert CJ, Caldwell AE, Kahng AB, Markov IL. Hypergraph partitioning with fixed vertices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 267-272. DOI: 10.1109/43.828555  0.572
1999 Alpert CJ, Caldwell AE, Chan TF, Huang DJ, Kahng AB, Markov IL, Moroz MS. Analytical Engines are Unnecessary in Top-down Partitioning-based Placement Vlsi Design. 10: 99-116. DOI: 10.1155/1999/93607  0.53
1999 Caldwell AE, Kahng AB, Mantik S, Markov IL, Zelikovsky A. On wirelength estimations for row-based placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1265-1278. DOI: 10.1109/43.784119  0.715
1999 Alpert CJ, Caldwell AE, Kahng AB, Markov IL. Partitioning with terminals: A `new' problem and new benchmarks Proceedings of the International Symposium On Physical Design. 151-157.  0.43
1998 Alpert CJ, Chan TF, Kahng AB, Markov IL, Mulet P. Faster minimization of linear wirelength for global placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 3-13. DOI: 10.1109/43.673628  0.53
1998 Kahng AB, Lach J, Mangione-Smith WH, Mantik S, Markov IL, Potkonjak M, Tucker P, Wang H, Wolfe G. Watermarking techniques for intellectual property protection Proceedings - Design Automation Conference. 776-781.  0.753
Low-probability matches (unlikely to be authored by this person)
2005 Chang KH, Markov IL, Bertacco V. Post-placement rewiring and rebuffering by exhaustive search for functional symmetries Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 56-63. DOI: 10.1109/ICCAD.2005.1560040  0.298
2012 Knechtel J, Markov IL, Lienig J. Assembling 2-D blocks into 3-D chips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 228-241. DOI: 10.1109/Tcad.2011.2174640  0.294
2013 Papa DA, Markov IL. Conclusions Lecture Notes in Electrical Engineering. 166: 149-155. DOI: 10.1007/978-1-4614-1356-1-10  0.292
2011 Markov IL, Shi Y. Constant-degree graph expansions that preserve treewidth Algorithmica (New York). 59: 461-470. DOI: 10.1007/S00453-009-9312-5  0.291
2009 Roy JA, Viswanathan N, Nam GJ, Alpert CJ, Markov IL. CRISP: Congestion reduction by iterated spreading during placement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 357-362.  0.289
2013 Papa DA, Markov IL. Logic restructuring as an aid to physical retiming Lecture Notes in Electrical Engineering. 166: 105-122. DOI: 10.1007/978-1-4614-1356-1-7  0.288
2003 Bullock SS, Markov IL. Arbitrary two-qubit computation in 23 elementary gates Physical Review a - Atomic, Molecular, and Optical Physics. 68. DOI: 10.1103/Physreva.68.012318  0.287
2005 Ng A, Markov IL. Toward quality EDA tools and tool flows through high-performance computing Proceedings - International Symposium On Quality Electronic Design, Isqed. 22-27. DOI: 10.1109/ISQED.2005.125  0.287
2015 Sabry Aly MM, Gao M, Hills G, Lee C, Pitner G, Shulaker MM, Wu TF, Asheghi M, Bokor J, Franchetti F, Goodson KE, Kozyrakis C, Markov I, Olukotun K, Pileggi L, et al. Energy-Efficient Abundant-Data Computing: The N3XT 1,000x Computer. 48: 24-33. DOI: 10.1109/Mc.2015.376  0.286
1999 Caldwell AE, Kahng AB, Markov IL. Optimal partitioners and end-case placers for standard-cell layout Proceedings of the International Symposium On Physical Design. 90-96.  0.286
2008 Plaza SM, Markov IL, Bertacco V. Random stimulus generation using entropy and XOR constraints Proceedings -Design, Automation and Test in Europe, Date. 664-669. DOI: 10.1109/DATE.2008.4484754  0.285
2008 Hu J, Roy JA, Markov IL. Sidewinder - A scalable ILP-based router International Workshop On System Level Interconnect Prediction, Slip. 73-79. DOI: 10.1145/1353610.1353625  0.285
2016 Mudge T, Chong FT, Markov IL, Sendag R, Yi JJ, Chiou D. Impact of Future Technologies on Architecture Ieee Micro. 36: 48-56. DOI: 10.1109/Mm.2016.71  0.283
2010 Papa DA, Krishnaswamy S, Markov IL. SPIRE: A retiming-based physical-synthesis transformation system Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 373-380. DOI: 10.1109/ICCAD.2010.5653647  0.283
2004 Aloul FA, Markov IL, Sakallah KA. MINCE: A static global variable-ordering heuristic for SAT search and BDD manipulation Journal of Universal Computer Science. 10: 1562-1596.  0.282
2005 Chant HH, Adya SN, Markov IL. Are floorplan representations important in digital design? Proceedings of the International Symposium On Physical Design. 129-136.  0.281
2007 Krishnaswamy S, Markov IL, Hayes JP. Tracking uncertainty with probabilistic logic circuit testing Ieee Design and Test of Computers. 24: 312-321. DOI: 10.1109/Mdt.2007.146  0.28
2013 Papa DA, Markov IL. Buffer insertion during timing-driven placement Lecture Notes in Electrical Engineering. 166: 21-46. DOI: 10.1007/978-1-4614-1356-1-3  0.278
2008 Moffitt MD, Roy JA, Markov IL. The coming of age of (academic) global routing Proceedings of the International Symposium On Physical Design. 148-155. DOI: 10.1145/1353629.1353662  0.278
2007 Chang KH, Markov IL, Bertacco V. Automating post>silicon debugging and repair Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 91-98. DOI: 10.1109/ICCAD.2007.4397249  0.277
2008 Roy JA, Koushanfar F, Markov IL. Protecting bus-based hardware IP by secret sharing Proceedings - Design Automation Conference. 846-851. DOI: 10.1109/DAC.2008.4555937  0.277
2000 Kennings AA, Markov IL. Analytical minimization of half-perimeter wirelength Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 179-184. DOI: 10.1145/368434.368600  0.276
2013 Katebi H, Sakallah KA, Markov IL. Generalized Boolean symmetries through nested partition refinement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 763-770. DOI: 10.1109/ICCAD.2013.6691200  0.271
2001 Adya SN, Markov IL. Fixed-outline floorplanning through better local search Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 328-334.  0.27
2011 Kim MC, Hu J, Lee DJ, Markov IL. A SimPLR method for routability-driven placement Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 67-73. DOI: 10.1109/ICCAD.2011.6105307  0.27
2010 Hu J, Roy JA, Markov IL. Completing high-quality global routes Proceedings of the International Symposium On Physical Design. 35-41. DOI: 10.1145/1735023.1735035  0.268
2012 Knechtel J, Markov IL, Lienig J, Thiele M. Multiobjective optimization of deadspace, a critical resource for 3D-IC integration Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 705-712.  0.266
2011 Markov IL. EDA: Synergy or sum of the parts? [review of "Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon" (Wang, L.-T., Eds., et al; 2009)] Ieee Design & Test of Computers. 28: 78-79. DOI: 10.1109/Mdt.2011.13  0.264
2012 Hu J, Kahng AB, Kang S, Kim MC, Markov IL. Sensitivity-guided metaheuristics for accurate discrete gate sizing Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 233-239.  0.263
2008 Roy JA, Koushanfar F, Markov IL. EPIC: Ending piracy of integrated circuits Proceedings -Design, Automation and Test in Europe, Date. 1069-1074. DOI: 10.1109/DATE.2008.4484823  0.26
2009 Chang KH, Papa DA, Markov IL, Bertacco V. Incremental verification with error detection, diagnosis, and visualization Ieee Design and Test of Computers. 26: 34-43. DOI: 10.1109/Mdt.2009.38  0.259
2002 Adya SN, Markov IL. Consistent placement of macro-blocks using floorplanning and standard-cell placement Proceedings of the International Symposium On Physical Design. 12-17.  0.256
2009 Chang KH, Bertacco V, Markov IL. Customizing IP cores for system-on-chip designs using extensive external don't-cares Proceedings -Design, Automation and Test in Europe, Date. 582-585.  0.253
2002 Shende VV, Prasad AK, Markov IL, Hayes JP. Reversible logic circuit synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 353-360. DOI: 10.1145/774572.774625  0.252
2013 Papa DA, Markov IL. Bounded transactional timing analysis Lecture Notes in Electrical Engineering. 166: 47-63. DOI: 10.1007/978-1-4614-1356-1-4  0.252
2013 Hu J, Kim MC, Markov IL. Taming the complexity of coordinated place and route Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488920  0.251
2004 Kahng AB, Markov IL, Reda S. On legalization of row-based placements Proceedings of the Acm Great Lakes Symposium On Vlsi. 214-219.  0.25
2013 Papa DA, Markov IL. Timing closure for multi-million-gate integrated circuits Lecture Notes in Electrical Engineering. 166: 3-9. DOI: 10.1007/978-1-4614-1356-1-1  0.249
2012 Markov IL, Saeedi M. Constant-optimized quantum circuits for modular multiplication and exponentiation Quantum Information and Computation. 12: 361-394.  0.248
2013 Papa DA, Markov IL. Gate sizing during timing-driven placement Lecture Notes in Electrical Engineering. 166: 65-80. DOI: 10.1007/978-1-4614-1356-1-5  0.248
2002 Aloul FA, Markov IL, Sakallah KA. Improving the efficiency of circuit-to-BDD conversion by gate and input ordering Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 64-69.  0.247
2008 Patel KN, Markov IL, Hayes JP. Optimal synthesis of linear reversible circuits Quantum Information and Computation. 8: 282-294.  0.246
2002 Aloul FA, Ramani A, Markov IL, Sakallah KA. Solving difficult SAT instances in the presence of symmetry Proceedings - Design Automation Conference. 731-736.  0.245
2007 Plaza SM, Chang KH, Markov IL, Bertacco V. Node mergers in the presence of don't cares Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 414-419. DOI: 10.1109/ASPDAC.2007.358021  0.242
2008 Krishnaswamy S, Markov IL, Hayes JP. On the role of timing masking in reliable logic circuit design Proceedings - Design Automation Conference. 924-929. DOI: 10.1109/DAC.2008.4555952  0.241
2006 Roy JA, Papa DA, Ng AN, Markov IL. Satisfying whitespace requirements in top-down placement Proceedings of the International Symposium On Physical Design. 2006: 206-208.  0.239
2010 Lee DJ, Kim MC, Markov IL. Low-power clock trees for CPUs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 444-451. DOI: 10.1109/ICCAD.2010.5653738  0.237
2002 Kennings AA, Markov IL. Smoothening max-terms and analytical minimization of half-perimeter wirelength Vlsi Design. 14: 229-237.  0.235
2007 Markov IL, Scheffer LK, Stroobandt D. Special issue on System-Level Interconnect Prediction Integration, the Vlsi Journal. 40: 381. DOI: 10.1016/J.Vlsi.2006.12.002  0.235
2013 Papa DA, Markov IL. State of the art in physical synthesis Lecture Notes in Electrical Engineering. 166: 11-18. DOI: 10.1007/978-1-4614-1356-1-2  0.234
2005 Aloulj FA, Ramani A, Markov IL, Sakallah KA. Dynamic symmetry-breaking for improved Boolean optimization Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 445-450.  0.232
2005 Krishnaswamy S, Viamontes GF, Markov IL, Hayes JP. Accurate reliability evaluation and enhancement via probabilistic transfer matrices Proceedings -Design, Automation and Test in Europe, Date '05. 282-287. DOI: 10.1109/DATE.2005.47  0.232
2004 Chan HH, Markov IL. Practical slicing and non-slicing block-packing without simulated annealing Proceedings of the Acm Great Lakes Symposium On Vlsi. 282-287.  0.231
2004 Aloul FA, Ramani A, Markov IL, Sakallah KA. ShatterPB: Symmetry-breaking for pseudo-Boolean formulas Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 884-887.  0.229
2007 Krishnaswamy S, Plaza SM, Markov IL, Hayes JP. Enhancing design robustness with reliability-aware resynthesis and logic simulation Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 149-154. DOI: 10.1109/ICCAD.2007.4397258  0.229
2011 Lee DJ, Markov IL. Multilevel tree fusion for robust clock networks Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 632-639. DOI: 10.1109/ICCAD.2011.6105396  0.226
2010 Yamashita S, Markov IL. Fast equivalence-checking for quantum circuits Quantum Information and Computation. 10: 721-734. DOI: 10.1109/NANOARCH.2010.5510932  0.226
2002 Motter DRB, Markov IL. A compressed breadth-first search for satisfiability Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 2409: 29-42.  0.226
2005 Markov IL, Maslov D. Uniformly-switching logic for cryptographic hardware Proceedings -Design, Automation and Test in Europe, Date '05. 432-433. DOI: 10.1109/DATE.2005.323  0.218
2005 Viamontes GF, Markov IL, Hayes JP. Is quantum search practical? Computing in Science and Engineering. 7: 62-70. DOI: 10.1109/MCSE.2005.53  0.214
2013 Markov IL. Know your limits (review of "limits to parallel computation: p-completeness theory"; greenlaw, r., et al; 1995) [book review] Ieee Design & Test of Computers. 30: 78-83. DOI: 10.1109/Mdat.2012.2237133  0.214
2010 Katebi H, Sakallah KA, Markov IL. Symmetry and satisfiability: An update Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 6175: 113-127. DOI: 10.1007/978-3-642-14186-7_11  0.214
2012 Katebi H, Sakallah KA, Markov IL. Conflict anticipation in the search for graph automorphisms Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 7180: 243-257. DOI: 10.1007/978-3-642-28717-6_20  0.21
2004 Shende VV, Markov IL, Bullock SS. Finding small two-qubit circuits Proceedings of Spie - the International Society For Optical Engineering. 5436: 348-359. DOI: 10.1117/12.542381  0.209
2007 Chang KH, Wagner I, Bertacco V, Markov IL. Automatic error diagnosis and correction for RTL designs Proceedings - Ieee International High-Level Design Validation and Test Workshop, Hldvt. 65-72. DOI: 10.1109/HLDVT.2007.4392789  0.209
2007 Viamontes GF, Markov IL, Hayes JP. Checking equivalence of quantum circuits and states Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 69-74. DOI: 10.1109/ICCAD.2007.4397246  0.208
2008 Chang KH, Markov IL, Bertacco V. Reap what you sow: Spare cells for post-silicon metal fix Proceedings of the International Symposium On Physical Design. 103-110. DOI: 10.1145/1353629.1353654  0.207
2013 Bahar I, Jones AK, Katkoori S, Madden PH, Marculescu D, Markov IL. 'Scaling' the impact of EDA education: Preliminary findings from the CCC workshop series on extreme scale design automation 2013 Ieee International Conference On Microelectronic Systems Education, Mse 2013. 64-67. DOI: 10.1109/MSE.2013.6566706  0.207
2005 Xiu Z, Papa DA, Chong P, Albrecht C, Kuehlmann A, Rutenbar RA, Markov IL. Early research experience with openaccess gear: An open source development environment for physical design Proceedings of the International Symposium On Physical Design. 94-100.  0.206
2013 Krishnaswamy S, Markov IL, Hayes JP. Design, analysis and test of logic circuits under uncertainty Lecture Notes in Electrical Engineering. 115: 1-123. DOI: 10.1007/978-90-481-9644-9_1  0.205
2010 Markov I. Master numerical tasks with ease [review of Advanced Excel for Scientific Data Analysis, 2nd ed. (de Levie, R.; 2008)] [Book reviews] Ieee Design & Test of Computers. 27: 93-95. DOI: 10.1109/Mdt.2010.22  0.203
2005 Ramani A, Markov IL. Automatically exploiting symmetries in constraint programming Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 3419: 98-112. DOI: 10.1007/11402763_8  0.202
2013 García HJ, Markov IL. Quipu: High-performance simulation of quantum circuits using stabilizer frames 2013 Ieee 31st International Conference On Computer Design, Iccd 2013. 404-410. DOI: 10.1109/ICCD.2013.6657072  0.198
2012 Markov I. Too much automation? [Two books reviewed] Ieee Design & Test of Computers. 29: 96-98. DOI: 10.1109/Mdt.2012.2186901  0.198
2003 Aloul FA, Markov IL, Sakallah KA. Shatter: Efficient symmetry-breaking for Boolean satisfiability Proceedings - Design Automation Conference. 836-839.  0.196
2008 Darga PT, Sakallah KA, Markov IL. Faster symmetry discovery using sparsity of symmetries Proceedings - Design Automation Conference. 149-154. DOI: 10.1109/DAC.2008.4555799  0.196
2012 Kim MC, Viswanathan N, Alpert CJ, Markov IL, Ramji S. MAPLE: Multilevel adaptive PLacEment for mixed-size designs Proceedings of the International Symposium On Physical Design. 193-200. DOI: 10.1145/2160916.2160958  0.195
2004 Shende VV, Markov IL, Bullock SS. Smaller two-qubit circuits for quantum communication and computation Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 980-985. DOI: 10.1109/DATE.2004.1269020  0.191
2010 Nadakuditi RR, Markov IL. On the costs and benefits of stochasticity in stream processing Proceedings - Design Automation Conference. 320-325. DOI: 10.1145/1837274.1837357  0.189
2015 Plaza SM, Markov IL. Protecting integrated circuits from piracy with test-aware logic locking Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2015: 262-269. DOI: 10.1109/ICCAD.2014.7001361  0.188
2008 Seo JS, Markov IL, Sylvester D, Blaauw D. On the decreasing significance of large standard cells in technology mapping Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 116-121. DOI: 10.1109/ICCAD.2008.4681561  0.188
2006 Das R, Markov IL, Hayes JP. On-chip test generation using linear subspaces Proceedings - Eleventh Ieee European Test Symposium, Ets 2006. 2006: 111-116. DOI: 10.1109/ETS.2006.35  0.184
2013 Codenotti P, Katebi H, Sakallah KA, Markov IL. Conflict analysis and branching heuristics in the search for graph automorphisms Proceedings - International Conference On Tools With Artificial Intelligence, Ictai. 907-914. DOI: 10.1109/ICTAI.2013.139  0.183
2013 Yao Y, Kim MB, Li J, Markov IL, Koushanfar F. ClockPUF: Physical unclonable functions based on clock networks Proceedings -Design, Automation and Test in Europe, Date. 422-427.  0.183
2011 Markov IL, Lee DJ. Algorithmic tuning of clock trees and derived non-tree structures Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 279-282. DOI: 10.1109/ICCAD.2011.6105342  0.182
2013 Papa DA, Markov IL. Physically-driven logic restructuring Lecture Notes in Electrical Engineering. 166: 83-103. DOI: 10.1007/978-1-4614-1356-1-6  0.179
2005 Shende VV, Bullock SS, Markov IL. Synthesis of quantum logic circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: 272-275.  0.178
2012 Chang KH, Chou HZ, Markov IL. RTL analysis and modifications for improving at-speed test Proceedings -Design, Automation and Test in Europe, Date. 400-405.  0.177
2009 Shende VV, Markov IL. On the cnot-cost of toffoli gates Quantum Information and Computation. 9: 461-486.  0.172
2003 Aloul FA, Markov IL, Sakallah KA. FORCE: A fast & easy-to-implement variable-ordering heuristic Proceedings of the Ieee Great Lakes Symposium On Vlsi. 116-119.  0.171
2002 Caldwell AE, Markov IL, Kahng AB. Toward CAD-IP reuse: A web bookshelf of fundamental algorithms Ieee Design and Test of Computers. 19: 72-81.  0.17
2009 Krishnaswamy S, Markov IL, Hayes JP. Improving testability and soft-error resilience through retiming Proceedings - Design Automation Conference. 508-513.  0.165
2008 Roy JA, Koushanfar F, Markov IL. Circuit CAD tools as a security threat 2008 Ieee International Workshop On Hardware-Oriented Security and Trust, Host. 65-66. DOI: 10.1109/HST.2008.4559052  0.159
2006 Papa DA, Markov IL, Chong P. Utility of the OpenAccess database in academic research Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 440-441.  0.149
2003 Viamontes GF, Rajagopalan M, Markov IL, Hayes JP. Gate-level simulation of quantum circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2003: 295-301. DOI: 10.1109/ASPDAC.2003.1195031  0.148
2011 Knechtel J, Markov IL, Lienig J. Assembling 2D blocks into 3D chips Proceedings of the International Symposium On Physical Design. 81-88. DOI: 10.1145/1960397.1960417  0.144
2004 Viamontes GF, Markov IL, Hayes JP. High-performance QuIDD-based simulation of quantum circuits Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1354-1355. DOI: 10.1109/DATE.2004.1269084  0.144
2013 Papa DA, Markov IL. Broadening the scope of optimization using partitioning Lecture Notes in Electrical Engineering. 166: 123-132. DOI: 10.1007/978-1-4614-1356-1-8  0.143
2004 Bullock SS, Markov IL. Asymptotically optimal circuits for arbitrary n-qubit diagonal comutations Quantum Information and Computation. 4: 27-47.  0.139
2010 García HJ, Markov IL. Spinto: High-performance energy minimization in spin glasses Proceedings -Design, Automation and Test in Europe, Date. 160-165.  0.138
2012 Kim MC, Markov IL. ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement Proceedings - Design Automation Conference. 747-755. DOI: 10.1145/2228360.2228496  0.129
2005 Krishnaswamy S, Markov IL, Hayes JP. Logic circuit testing for transient faults Proceedings of the 10th Ieee European Test Symposium, Ets 2005. 2005: 102-107. DOI: 10.1109/ETS.2005.27  0.127
2004 Oh Y, Mneimneh MN, Andraus ZS, Sakallah KA, Markov IL. AMUSE: A minimally-unsatisfiable subformula extractor Proceedings - Design Automation Conference. 518-523.  0.125
2014 García HJ, Markov IL, Cross AW. On the geometry of stabilizer states Quantum Information and Computation. 14: 683-720.  0.107
2004 Papa DA, Adya SN, Markov IL. Constructive benchmarking for placement Proceedings of the Acm Great Lakes Symposium On Vlsi. 113-118.  0.107
2003 Bullock SS, Markov IL. An arbitrary two-qubit computation in 23 elementary gates or less Proceedings - Design Automation Conference. 324-329.  0.106
2009 Viamontes GF, Markov IL, Hayes JP. Quantum circuit simulation Quantum Circuit Simulation. 1-190. DOI: 10.1007/978-90-481-3065-8  0.099
2002 Aloul FA, Ramani A, Markov IL, Sakallah KA. Generic ILP versus specialized 0-1 ILP: An update Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 450-457. DOI: 10.1145/774572.774638  0.098
2005 Shende VV, Markov IL. Quantum circuits for incompletely specified two-qubit operators Quantum Information and Computation. 5: 49-57.  0.093
2019 Sabry Aly MM, Wu TF, Bartolo A, Malviya YH, Hwang W, Hills G, Markov I, Wootters M, Shulaker MM, Philip Wong H, Mitra S. The N3XT Approach to Energy-Efficient Abundant-Data Computing Proceedings of the Ieee. 107: 19-48. DOI: 10.1109/JPROC.2018.2882603  0.092
1999 Alpert CJ, Caldwell AE, Chan TF, Huang DJH, Kahng AB, Markov IL, Moroz MS. Analytical Engines are Unnecessary in Top-down Partitioning-based Placement Vlsi Design. 10: 99-116.  0.084
2015 Wang M, Yates A, Markov IL. SuperPUF: Integrating heterogeneous Physically Unclonable Functions Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2015: 454-461. DOI: 10.1109/ICCAD.2014.7001391  0.082
2003 Adya SN, Markov IL, Villarrubia PG. On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 311-318.  0.076
2015 Markov IL, Hu J, Kim MC. Progress and Challenges in VLSI Placement Research Proceedings of the Ieee. DOI: 10.1109/JPROC.2015.2478963  0.076
2001 Aloul FA, Markov IL, Sakallah KA. Faster SAT and smaller BDDS via common function structure Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 443-448.  0.053
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