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Ioannis Savidis, Ph.D. - Publications

Affiliations: 
2013 Hajim School of Engineering and Applied Sciences University of Rochester, Rochester, NY 
 2013- Electrical and Computer Engineering Drexel University, Philadelphia, PA, United States 
Area:
Electronics and Electrical Engineering, General Engineering
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24 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Juretus K, Savidis I. Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1607-1620. DOI: 10.1109/Tcad.2019.2925387  0.323
2020 Hossain MS, Savidis I. Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing Microelectronics Journal. 102: 104801. DOI: 10.1016/J.Mejo.2020.104801  0.366
2020 Hossain MS, Savidis I. Recycling of unused leakage current for energy efficient multi-voltage systems Microelectronics Journal. 101: 104782. DOI: 10.1016/J.Mejo.2020.104782  0.395
2018 Pathak D, Savidis I. On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 2230-2240. DOI: 10.1109/Tvlsi.2018.2856087  0.428
2018 Khavari Tavana M, Hajkazemi MH, Pathak D, Savidis I, Homayoun H. ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 26: 249-261. DOI: 10.1109/Tvlsi.2017.2759219  0.348
2017 Pathak D, Homayoun H, Savidis I. Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 25: 2538-2551. DOI: 10.1109/Tvlsi.2017.2699644  0.384
2016 Savidis I, Ciftcioglu B, Xu J, Hu J, Jain M, Berman R, Xue J, Liu P, Moore D, Wicks G, Huang M, Wu H, Friedman EG. Heterogeneous 3-D circuits: Integrating free-space optics with CMOS Microelectronics Journal. 50: 66-75. DOI: 10.1016/J.Mejo.2015.10.004  0.691
2015 Savidis I, Vaisband B, Friedman EG. Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2077-2089. DOI: 10.1109/Tvlsi.2014.2357441  0.675
2014 Pathak D, Savidis I. Run-time voltage detection circuit for 3-D IC power delivery International System On Chip Conference. 183-187. DOI: 10.1109/SOCC.2014.6948923  0.39
2014 Pathak D, Savidis I. Power supply voltage detection and clamping circuit for 3-D integrated circuits 2014 Soi-3d-Subthreshold Microelectronics Technology Unified Conference, S3s 2014. DOI: 10.1109/S3S.2014.7028202  0.318
2014 Vaisband B, Savidis I, Friedman EG. Thermal conduction path analysis in 3-D ICs Proceedings - Ieee International Symposium On Circuits and Systems. 594-597. DOI: 10.1109/ISCAS.2014.6865205  0.609
2013 Savidis I, Kose S, Friedman EG. Power noise in TSV-based 3-D integrated circuits Ieee Journal of Solid-State Circuits. 48: 587-597. DOI: 10.1109/Jssc.2012.2217891  0.735
2012 Ciftcioglu B, Berman R, Wang S, Hu J, Savidis I, Jain M, Moore D, Huang M, Friedman EG, Wicks G, Wu H. 3-D integrated heterogeneous intra-chip free-space optical interconnect. Optics Express. 20: 4331-45. PMID 22418191 DOI: 10.1364/Oe.20.004331  0.605
2012 Wu H, Ciftcioglu B, Berman R, Hu J, Wang S, Savidis I, Jain M, Moore D, Huang M, Friedman EG, Wicks G. Chip-scale demonstration of 3-D integrated intra-chip free-space optical interconnect Proceedings of Spie - the International Society For Optical Engineering. 8265. DOI: 10.1117/12.913314  0.616
2011 Pavlidis VF, Savidis I, Friedman EG. Clock distribution networks in 3-D integrated systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 2256-2266. DOI: 10.1109/Tvlsi.2010.2073724  0.764
2011 Ciftcioglu B, Berman R, Zhang J, Darling Z, Wang S, Hu J, Xue J, Garg A, Jain M, Savidis I, Moore D, Huang M, Friedman EG, Wicks G, Wu H. A 3-D integrated intrachip free-space optical interconnect for many-core chips Ieee Photonics Technology Letters. 23: 164-166. DOI: 10.1109/Lpt.2010.2093876  0.595
2011 Savidis I, Pavlidis V, Friedman EG. Clock distribution models of 3-D integrated systems Proceedings - Ieee International Symposium On Circuits and Systems. 2225-2228. DOI: 10.1109/ISCAS.2011.5938043  0.635
2011 Wang J, Savidis I, Friedman EG. Thermal analysis of oxide-confined VCSEL arrays Microelectronics Journal. 42: 820-825. DOI: 10.1016/J.Mejo.2010.11.005  0.561
2010 Xue J, Garg A, Ciftcioglu B, Hu J, Wang S, Savidis I, Jain M, Berman R, Liu P, Huang M, Wu H, Friedman E, Wicks G, Moore D. An intra-chip free-space optical interconnect Proceedings - International Symposium On Computer Architecture. 94-105. DOI: 10.1145/1815961.1815975  0.526
2010 Savidis I, Alam SM, Jain A, Pozder S, Jones RE, Chatterjee R. Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits Microelectronics Journal. 41: 9-16. DOI: 10.1016/J.Mejo.2009.10.006  0.601
2009 Savidis I, Friedman EG. Closed-form expressions of 3-D via resistance, inductance, and capacitance Ieee Transactions On Electron Devices. 56: 1873-1881. DOI: 10.1109/Ted.2009.2026200  0.59
2008 Pavlidis VF, Savidis I, Friedman EG. Clock distribution architectures for 3-D SOI integrated circuits Proceedings - Ieee International Soi Conference. 111-112. DOI: 10.1109/SOI.2008.4656319  0.74
2008 Savidis I, Friedman EG. Electrical modeling and characterization of 3-D vias Proceedings - Ieee International Symposium On Circuits and Systems. 784-787. DOI: 10.1109/ISCAS.2008.4541535  0.61
2008 Pavlidis VF, Savidis I, Friedman EG. Clock distribution networks for 3-D integrated circuits Proceedings of the Custom Integrated Circuits Conference. 651-654. DOI: 10.1109/CICC.2008.4672170  0.771
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