☰

Gu-yeon Wei, Ph.D. - Publications

Affiliations: 
Electrical Engineering Harvard University, Cambridge, MA, United States 
 2001 Stanford University, Palo Alto, CA 
Area:
Electrical Engineering, Computer science
Tree Info Grants Similar researchers PubMed Report error

41 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Whatmough PN, Donato M, Ko GG, Lee SK, Brooks D, Wei G. CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development Ieee Micro. 40: 32-40. DOI: 10.1109/Mm.2020.2995809  0.406
2020 Mattson P, Tang H, Wei G, Wu C, Reddi VJ, Cheng C, Coleman C, Diamos G, Kanter D, Micikevicius P, Patterson D, Schmuelling G. MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance Ieee Micro. 40: 8-16. DOI: 10.1109/Mm.2020.2974843  0.302
2019 Wang Y, Lee V, Wei G, Brooks D. Predicting New Workload or CPU Performance by Analyzing Public Datasets Acm Transactions On Architecture and Code Optimization. 15: 53. DOI: 10.1145/3284127  0.368
2019 Donato M, Pentecost L, Brooks D, Wei G. MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge Ieee Micro. 39: 73-81. DOI: 10.1109/Mm.2019.2944782  0.346
2019 Ma S, Donato M, Lee SK, Brooks D, Wei G. Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights Ieee Electron Device Letters. 40: 1403-1406. DOI: 10.1109/Led.2019.2930212  0.368
2019 Bhardwaj K, Havasi M, Yao Y, Brooks DM, Lobato JMH, Wei G. Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization Ieee Computer Architecture Letters. 18: 119-123. DOI: 10.1109/Lca.2019.2910521  0.358
2019 Lee SK, Whatmough PN, Brooks D, Wei G. A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs Ieee Journal of Solid-State Circuits. 54: 1982-1992. DOI: 10.1109/Jssc.2019.2913098  0.517
2018 Lok M, Helbling EF, Zhang X, Wood R, Brooks D, Wei G. A Low Mass Power Electronics Unit to Drive Piezoelectric Actuators for Flying Microrobots Ieee Transactions On Power Electronics. 33: 3180-3191. DOI: 10.1109/Tpel.2017.2704290  0.459
2018 Garibotti R, Reagen B, Shao YS, Wei G, Brooks D. Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 1440-1444. DOI: 10.1109/Tcsii.2018.2860122  0.378
2018 Chaput S, Brooks D, Wei G. An Area-Efficient 8-Bit Single-Ended ADC With Extended Input Voltage Range Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 1549-1553. DOI: 10.1109/Tcsii.2017.2759777  0.473
2018 Whatmough PN, Lee SK, Brooks D, Wei G. DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications Ieee Journal of Solid-State Circuits. 53: 2722-2731. DOI: 10.1109/Jssc.2018.2841824  0.391
2017 Campanoni S, Brownell K, Kanev S, Jones TM, Wei G, Brooks D. Automatically accelerating non-numerical programs by architecture-compiler co-design Communications of the Acm. 60: 88-97. DOI: 10.1145/3139461  0.378
2017 Lee SK, Tong T, Zhang X, Brooks D, Wei G. A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC–DC Converter Ieee Transactions On Very Large Scale Integration Systems. 25: 1271-1284. DOI: 10.1109/Tvlsi.2016.2633805  0.465
2017 Zhang X, Lok M, Tong T, Lee SK, Reagen B, Chaput S, Duhamel PJ, Wood RJ, Brooks D, Wei G. A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle Ieee Journal of Solid-State Circuits. 52: 2374-2387. DOI: 10.1109/Jssc.2017.2705170  0.439
2016 Tong T, Lee SK, Zhang X, Brooks D, Wei G. A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications Ieee Journal of Solid-State Circuits. 51: 2142-2152. DOI: 10.1109/Jssc.2016.2580598  0.426
2015 Shao YS, Reagen B, Wei GY, Brooks D. The Aladdin Approach to Accelerator Design and Modeling Ieee Micro. 35: 58-70. DOI: 10.1109/Mm.2015.50  0.449
2015 Chung H, Deniz ZT, Rylyakov A, Bulzacchelli J, Friedman D, Wei GY. A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS Analog Integrated Circuits and Signal Processing. DOI: 10.1007/S10470-015-0624-X  0.575
2014 Chung H, Wei G. ADC-Based Backplane Receiver Design-Space Exploration Ieee Transactions On Very Large Scale Integration Systems. 22: 1539-1547. DOI: 10.1109/Tvlsi.2013.2275742  0.584
2014 Zhang X, Tong T, Brooks DM, Wei G. Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip Ieee Transactions On Circuits and Systems. 61: 2309-2317. DOI: 10.1109/Tcsi.2014.2312490  0.482
2013 Lyons M, Wei G, Brooks D. Shrink-Fit: A Framework for Flexible Accelerator Sizing Ieee Computer Architecture Letters. 12: 17-20. DOI: 10.1109/L-Ca.2012.7  0.407
2012 Campanoni S, Jones TM, Holloway G, Wei GY, Brooks D. Helix: Making the extraction of thread-level parallelism mainstream Ieee Micro. 32: 8-18. DOI: 10.1109/Mm.2012.50  0.339
2012 Kim W, Brooks D, Wei G. A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS Ieee Journal of Solid-State Circuits. 47: 206-219. DOI: 10.1109/Jssc.2011.2169309  0.438
2012 Karpelson M, Wei GY, Wood RJ. Driving high voltage piezoelectric actuators in microrobotic applications Sensors and Actuators, a: Physical. 176: 78-89. DOI: 10.1016/J.Sna.2011.11.035  0.492
2011 Brownell KM, Khan AD, Wei GY, Brooks D. Automating design of voltage interpolation to address process variations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 383-396. DOI: 10.1109/Tvlsi.2009.2034457  0.489
2011 Reddi VJ, Kanev S, Kim W, Campanoni S, Smith MD, Wei G, Brooks D. Voltage Noise in Production Processors Ieee Micro. 31: 20-28. DOI: 10.1109/Mm.2010.104  0.546
2011 Hempstead M, Brooks D, Wei G. An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 1: 193-202. DOI: 10.1109/Jetcas.2011.2160751  0.361
2010 Reddi VJ, Campanoni S, Gupta MS, Smith MD, Wei GY, Brooks D, Hazelwood K. Eliminating voltage emergencies via software-guided code transformations Transactions On Architecture and Code Optimization. 7. DOI: 10.1145/1839667.1839674  0.576
2010 Reddi VJ, Gupta M, Holloway G, Smith MD, Wei G, Brooks D. Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity Ieee Micro. 30: 110-110. DOI: 10.1109/Mm.2010.25  0.525
2010 Lyons M, Hempstead M, Wei G, Brooks D. The Accelerator Store framework for high-performance, low-power accelerator-based systems Ieee Computer Architecture Letters. 9: 53-56. DOI: 10.1109/L-Ca.2010.16  0.345
2009 Agrawal A, Liu A, Hanumolu PK, Wei GY. An 8× 5 Gb/s parallel receiver with collaborative timing recovery Ieee Journal of Solid-State Circuits. 44: 3120-3130. DOI: 10.1109/Jssc.2009.2033399  0.595
2008 Hempstead M, Lyons MJ, Brooks D, Wei GY. Survey of hardware systems for wireless sensor networks Journal of Low Power Electronics. 4: 11-20. DOI: 10.1166/Jolpe.2008.156  0.314
2008 Liang X, Canal R, Wei G, Brooks D. Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability Ieee Micro. 28: 60-68. DOI: 10.1109/Mm.2008.12  0.314
2008 Ratnayake R, Kavcic A, Wei G. A High-Throughput Maximum a Posteriori Probability Detector Ieee Journal of Solid-State Circuits. 43: 1846-1858. DOI: 10.1109/Jssc.2008.925404  0.374
2008 Helal BM, Straayer MZ, Wei G, Perrott MH. A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance Ieee Journal of Solid-State Circuits. 43: 855-863. DOI: 10.1109/Jssc.2008.917372  0.489
2008 Hanumolu PK, Wei GY, Moon UK. A wide-tracking range clock and data recovery circuit Ieee Journal of Solid-State Circuits. 43: 425-438. DOI: 10.1109/Jssc.2007.914290  0.426
2008 Hanumolu PK, Kratyuk V, Wei GY, Moon UK. A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter Ieee Journal of Solid-State Circuits. 43: 414-423. DOI: 10.1109/Jssc.2007.914287  0.393
2005 Hanumolu PK, Wei GY, Moon YK. Equalizers for high-speed serial links International Journal of High Speed Electronics and Systems. 15: 429-458. DOI: 10.1142/S0129156405003259  0.434
2003 Hanumolu PK, Casper B, Mooney R, Wei GY, Moon UK. Analysis of PLL Clock Jitter in High-Speed Serial Links Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 879-886. DOI: 10.1109/Tcsii.2003.819121  0.356
2003 Kim J, Horowitz MA, Wei G. Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 860-869. DOI: 10.1109/Tcsii.2003.819120  0.656
2003 Stonick JT, Wei G, Sonntag JL, Weinlader DK. An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS Ieee Journal of Solid-State Circuits. 38: 436-443. DOI: 10.1109/Jssc.2002.808282  0.388
1999 Wei G, Horowitz M. A fully digital, energy-efficient, adaptive power-supply regulator Ieee Journal of Solid-State Circuits. 34: 520-528. DOI: 10.1109/4.753685  0.624
Show low-probability matches.