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Un-Ku Moon - Publications

Affiliations: 
Electrical and Computer Engineering Oregon State University, Corvallis, OR 
Area:
Electronics and Electrical Engineering
Website:
https://web.engr.oregonstate.edu/~moon/
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184 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2021 Lee CY, Venkatachala PK, ElShater A, Moon U. A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators Ieee Transactions On Circuits and Systems Ii: Express Briefs. 68: 2327-2331. DOI: 10.1109/TCSII.2021.3060011  0.31
2020 Xu Y, Venkatachala PK, Hu Y, Leuenberger S, Temes GC, Moon U. A Charge-Domain Switched-G m -C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique Ieee Transactions On Circuits and Systems I-Regular Papers. 67: 600-610. DOI: 10.1109/Tcsi.2019.2949018  0.436
2020 Xu Y, Hu H, Muhlestein J, Moon U. A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter Ieee Journal of Solid-State Circuits. 1-1. DOI: 10.1109/Jssc.2020.3006790  0.355
2020 Sun H, Sobue K, Hamashita K, Anand T, Moon U. A 951-fs rms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator Ieee Journal of Solid-State Circuits. 55: 426-438. DOI: 10.1109/Jssc.2019.2952852  0.447
2019 He T, Kareppagoudr M, Zhang Y, Caceres E, Moon U, Temes GC. Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits Ieee Transactions On Circuits and Systems I-Regular Papers. 66: 1331-1341. DOI: 10.1109/Tcsi.2018.2885802  0.498
2019 ElShater A, Venkatachala PK, Lee CY, Muhlestein J, Leuenberger S, Sobue K, Hamashita K, Moon U. A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier Ieee Journal of Solid-State Circuits. 54: 3410-3420. DOI: 10.1109/Jssc.2019.2943935  0.484
2018 Sun H, Sobue K, Hamashita K, Moon U. An Oversampling Stochastic ADC Using VCO-Based Quantizers Ieee Transactions On Circuits and Systems I-Regular Papers. 65: 4037-4050. DOI: 10.1109/Tcsi.2018.2836466  0.51
2018 Xu Y, Moon U. A chopper-stabilized source follower coupling based low-pass filter with noise reduction Analog Integrated Circuits and Signal Processing. 95: 365-369. DOI: 10.1007/S10470-018-1185-6  0.507
2016 Waters A, Muhlestein J, Moon U. Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs Ieee Transactions On Circuits and Systems. 63: 1898-1909. DOI: 10.1109/Tcsi.2016.2594256  0.389
2016 Xu Y, Venkatachala PK, Leuenberger S, Moon UK. A 7.5mW 35-70MHz 4th-order semi-passive charge-sharing band-pass filter with programmable bandwidth and 72dB stop-band rejection in 65nm CMOS Digest of Papers - Ieee Radio Frequency Integrated Circuits Symposium. 2016: 162-165. DOI: 10.1109/RFIC.2016.7508276  0.318
2016 Muhlestein J, Venkatram H, Guerber J, Waters A, Moon UK. Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2016: 421-424. DOI: 10.1109/ICECS.2015.7440338  0.752
2016 Sun H, Muhlestein J, Moon UK. A VCO-based spatial averaging stochastic ADC Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 2016: 272-275. DOI: 10.1109/ICECS.2015.7440301  0.303
2016 Xu Y, Moon U. Charge-domain switched-g m-C CBPF using semi-passive charge-sharing technique Electronics Letters. 52: 1667-1669. DOI: 10.1049/El.2016.0942  0.411
2015 Hu Y, Venkatram H, Maghari N, Moon UK. A Continuous-Time Δ σ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 1063-1067. DOI: 10.1109/Tcsii.2015.2457011  0.718
2015 Xu Y, Sun H, Moon UK. Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency Midwest Symposium On Circuits and Systems. 2015. DOI: 10.1109/MWSCAS.2015.7282168  0.346
2015 Sun H, Moon UK. MDLL/PLL dual-path clock generator Midwest Symposium On Circuits and Systems. 2015. DOI: 10.1109/MWSCAS.2015.7282044  0.359
2015 Xu Y, Leuenberger S, Moon UK. Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 2033-2036. DOI: 10.1109/ISCAS.2015.7169076  0.458
2015 Leuenberger S, Moon UK. A single OpAmp 2nd-Order ΔΣ ADC with a double integrating quantizer Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 309-312. DOI: 10.1109/ISCAS.2015.7168632  0.4
2015 Leuenberger S, Waters A, Moon UK. Resistive correction of low output impedance high-speed current-steering DACs 2014 21st Ieee International Conference On Electronics, Circuits and Systems, Icecs 2014. 459-462. DOI: 10.1109/ICECS.2014.7050021  0.341
2015 Waters A, Leuenberger S, Farahbakhshian F, Moon UK. Analysis and performance trade-offs of linearity calibration for stochastic ADCs 2014 21st Ieee International Conference On Electronics, Circuits and Systems, Icecs 2014. 207-210. DOI: 10.1109/ICECS.2014.7049958  0.326
2014 Weaver S, Hershberg B, Moon UK. Digitally synthesized stochastic flash ADC using only standard digital cells Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 84-91. DOI: 10.1109/Tcsi.2013.2268571  0.834
2014 Gande M, Venkatram H, Lee HY, Guerber J, Moon UK. Blind calibration algorithm for nonlinearity correction based on selective sampling Ieee Journal of Solid-State Circuits. 49: 1715-1724. DOI: 10.1109/Jssc.2014.2321163  0.79
2014 Oh T, Venkatram H, Moon UK. A time-based pipelined ADC using both voltage and time domain information Ieee Journal of Solid-State Circuits. 49: 961-971. DOI: 10.1109/Jssc.2013.2293019  0.645
2014 Hu Y, Farahbakhshian F, Moon UK. Time amplifiers based on phase accumulation Proceedings - Ieee International Symposium On Circuits and Systems. 2349-2352. DOI: 10.1109/ISCAS.2014.6865643  0.344
2014 Maghari N, Moon UK. Emerging analog-to-digital converters European Solid-State Circuits Conference. 43-50. DOI: 10.1109/ESSCIRC.2014.6942019  0.708
2014 Hu Y, Xu Y, Moon UK. Inherently linear time symmetric pulse width modulation Proceedings of the Ieee 2014 Custom Integrated Circuits Conference, Cicc 2014. DOI: 10.1109/CICC.2014.6946125  0.392
2013 Venkatram H, Guerber J, Gande M, Moon UK. Detection and correction methods for single event effects in analog to digital converters Ieee Transactions On Circuits and Systems I: Regular Papers. 60: 3163-3172. DOI: 10.1109/Tcsi.2013.2265963  0.766
2013 Oh T, Maghari N, Moon UK. A second-order ΔΣ ADC using noise-shaped two-step integrating quantizer Ieee Journal of Solid-State Circuits. 48: 1465-1474. DOI: 10.1109/Jssc.2013.2257491  0.813
2013 Rajaee O, Moon UK. Highly linear noise-shaped pipelined ADC utilizing a relaxed accuracy front-end Ieee Journal of Solid-State Circuits. 48: 502-515. DOI: 10.1109/Jssc.2012.2227605  0.838
2013 Gande M, Guerber J, Moon UK. Analysis of back-end flash in a 1.5b/stage pipelined ADC Proceedings - Ieee International Symposium On Circuits and Systems. 2247-2250. DOI: 10.1109/ISCAS.2013.6572324  0.758
2013 Gande M, Lee HY, Venkatram H, Guerber J, Moon UK. Blind background calibration of harmonic distortion based on selective sampling Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2013.6658441  0.753
2013 Guerber J, Venkatram H, Gande M, Moon U. Ternary R2R DAC design for improved energy efficiency Electronics Letters. 49: 329-330. DOI: 10.1049/El.2012.4224  0.763
2013 Hershberg B, Moon UK. A 75.9dB-SNDR 2.96mW 29fJ/conv-step ringamp-only pipelined ADC Ieee Symposium On Vlsi Circuits, Digest of Technical Papers.  0.373
2013 Oh T, Venkatram H, Moon UK. A 70MS/s 69.3dB SNDR 38.2fJ/conversion-step time-based pipelined ADC Ieee Symposium On Vlsi Circuits, Digest of Technical Papers.  0.444
2012 Gande M, Maghari N, Oh T, Moon UK. A 71dB dynamic range third-order ΔΣ TDC using charge-pump Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 168-169. DOI: 10.1109/VLSIC.2012.6243843  0.765
2012 Oh T, Maghari N, Moon UK. A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 162-163. DOI: 10.1109/VLSIC.2012.6243840  0.764
2012 Sasidhar N, Gubbins D, Hanumolu PK, Moon UK. Rail-to-rail input pipelined ADC incorporating multistage signal mapping Ieee Transactions On Circuits and Systems Ii: Express Briefs. 59: 558-562. DOI: 10.1109/Tcsii.2012.2208668  0.49
2012 Guerber J, Gande M, Moon UK. The analysis and application of redundant multistage ADC resolution improvements through PDF residue shaping Ieee Transactions On Circuits and Systems I: Regular Papers. 59: 1733-1742. DOI: 10.1109/Tcsi.2011.2180435  0.785
2012 Guerber J, Venkatram H, Gande M, Waters A, Moon UK. A 10-b ternary SAR ADC with quantization time information utilization Ieee Journal of Solid-State Circuits. 47: 2604-2613. DOI: 10.1109/Jssc.2012.2211696  0.818
2012 Lee HY, Lee B, Moon UK. A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 474-475. DOI: 10.1109/ISSCC.2012.6177097  0.376
2012 Hershberg B, Musah T, Weaver S, Moon UK. The effect of correlated level shifting on noise performance in switched capacitor circuits Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 942-945. DOI: 10.1109/ISCAS.2012.6272200  0.807
2012 Oh T, Venkatram H, Guerber J, Moon UK. Correlated jitter sampling for jitter cancellation in pipelined TDC Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 810-813. DOI: 10.1109/ISCAS.2012.6272164  0.767
2012 Venkatram H, Oh T, Guerber J, Moon UK. Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 428-431. DOI: 10.1109/ISCAS.2012.6272055  0.789
2012 Guerber J, Venkatram H, Oh T, Moon UK. Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm Iscas 2012 - 2012 Ieee International Symposium On Circuits and Systems. 2361-2364. DOI: 10.1109/ISCAS.2012.6271770  0.784
2011 Weaver S, Hershberg B, Maghari N, Moon UK. Domino-logic-based ADC for digital synthesis Ieee Transactions On Circuits and Systems Ii: Express Briefs. 58: 744-747. DOI: 10.1109/Tcsii.2011.2168019  0.84
2011 Oh T, Maghari N, Gubbins D, Moon UK. Analysis of residue integration sampling with improved jitter immunity Ieee Transactions On Circuits and Systems Ii: Express Briefs. 58: 417-421. DOI: 10.1109/Tcsii.2011.2158273  0.768
2011 Vytyaz I, Hanumolu PK, Moon UK, Mayaram K. Design-oriented analysis of circuits with equality constraints Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1089-1098. DOI: 10.1109/Tcsi.2010.2090570  0.378
2011 Maghari N, Moon UK. A third-order DT ΔΣ modulator using noise-shaped bi-directional single-slope quantizer Ieee Journal of Solid-State Circuits. 46: 2882-2891. DOI: 10.1109/Jssc.2011.2164964  0.788
2011 Rajaee O, Takeuchi S, Aniya M, Hamashita K, Moon UK. Low-OSR over-ranging hybrid ADC incorporating noise-shaped two-step quantizer Ieee Journal of Solid-State Circuits. 46: 2458-2468. DOI: 10.1109/Jssc.2011.2164293  0.854
2011 Maghari N, Moon UK. A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 474-475. DOI: 10.1109/ISSCC.2011.5746403  0.743
2011 Lee HY, Gubbins D, Lee B, Moon UK. A 0.7V 810μW 10b 30MS/s comparator-based two-step pipelined ADC Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055326  0.388
2011 Guerber J, Gande M, Venkatram H, Waters A, Moon UK. A 10b Ternary SAR ADC with decision time quantization based redundancy 2011 Proceedings of Technical Papers: Ieee Asian Solid-State Circuits Conference 2011, a-Sscc 2011. 65-68. DOI: 10.1109/ASSCC.2011.6123605  0.778
2011 Gregoire BR, Musah T, Maghari N, Weaver S, Moon UK. A 30% beyond V DD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp 2011 Proceedings of Technical Papers: Ieee Asian Solid-State Circuits Conference 2011, a-Sscc 2011. 345-348. DOI: 10.1109/ASSCC.2011.6123585  0.818
2011 Musah T, Moon UK. Correlated level shifting integrator with reduced sensitivity to amplifier gain Electronics Letters. 47: 91-92. DOI: 10.1049/El.2010.2045  0.78
2011 Rajaee O, Moon U. A 12-ENOB 6X-OSR noise-shaped pipelined ADC utilizing a 9-bit linear front-end Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 34-35.  0.822
2010 Weaver S, Hershberg B, Kurahashi P, Knierim D, Moon UK. Stochastic flash analog-to-digital conversion Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 2825-2833. DOI: 10.1109/Tcsi.2010.2050225  0.799
2010 Hershberg B, Weaver S, Moon UK. Design of a split-CLS pipelined ADC with full signal swing using an accurate but fractional signal swing opamp Ieee Journal of Solid-State Circuits. 45: 2623-2633. DOI: 10.1109/JSSC.2010.2073190  0.431
2010 Gubbins D, Lee B, Hanumolu PK, Moon UK. Continuous-time input pipeline ADCs Ieee Journal of Solid-State Circuits. 45: 1456-1468. DOI: 10.1109/Jssc.2010.2048137  0.488
2010 Rajaee O, Musah T, Maghari N, Takeuchi S, Aniya M, Hamashita K, Moon UK. Design of a 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipelined ADC Ieee Journal of Solid-State Circuits. 45: 719-730. DOI: 10.1109/Jssc.2010.2042246  0.832
2010 Peach CT, Moon UK, Allstot DJ. An 11.1 mW 42 MS/s 10 b ADC with two-step settling in 0.18 μm CMOS Ieee Journal of Solid-State Circuits. 45: 391-400. DOI: 10.1109/Jssc.2009.2038123  0.481
2010 Hershberg BP, Weaver ST, Moon UK. A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 302-303. DOI: 10.1109/ISSCC.2010.5433894  0.827
2010 Maghari N, Moon UK. Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 297-300. DOI: 10.1109/ISCAS.2010.5537858  0.709
2010 Maghari N, Moon UK. A double-sampled path-coupled single-loop ΔΣ modulator using noise-shaped integrating quantizer Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 4005-4008. DOI: 10.1109/ISCAS.2010.5537654  0.745
2010 Musah T, Moon UK. Pseudo-differential zero-crossing-based circuit with differential error suppression Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 1731-1734. DOI: 10.1109/ISCAS.2010.5537538  0.778
2010 Rajaee O, Hu Y, Gande M, Musah T, Moon UK. An interstage correlated double sampling technique for switched-capacitor gain stages Iscas 2010 - 2010 Ieee International Symposium On Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 1252-1255. DOI: 10.1109/ISCAS.2010.5537279  0.809
2010 Venkatram H, Inti R, Moon UK. Least Mean Square calibration method for VCO non-linearity Proceedings of the International Conference On Microelectronics, Icm. 1-4. DOI: 10.1109/ICM.2010.5696115  0.382
2010 Venkatram H, Hershberg B, Moon UK. Asynchronous CLS for zero crossing based circuits 2010 Ieee International Conference On Electronics, Circuits, and Systems, Icecs 2010 - Proceedings. 1025-1028. DOI: 10.1109/ICECS.2010.5724689  0.332
2010 Maghari N, Weaver S, Moon UK. A +5dBFS third-order extended dynamic range single-loop ΔΣ modulator Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617593  0.778
2010 Rajaee O, Takeuchi S, Aniya M, Hamashita K, Moon U. A 1.2V, 78dB HDSP ADC with 3.1V input signal range 2010 Ieee Asian Solid-State Circuits Conference, a-Sscc 2010. 353-356. DOI: 10.1109/ASSCC.2010.5716628  0.846
2010 Hariprasath V, Guerber J, Lee SH, Moon UK. Merged capacitor switching based SAR ADC with highest switching energy-efficiency Electronics Letters. 46: 620-621. DOI: 10.1049/El.2010.0706  0.768
2010 Hu Y, Maghari N, Musah T, Moon U. Time-interleaved noise-shaping integrating quantisers Electronics Letters. 46: 757-758. DOI: 10.1049/El.2010.0656  0.815
2009 Carusone AC, Ismail Y, Moon U, Schmid H, Serdijn WA, Setti G. Guest Editorial Special Issue on ISCAS 2008 Ieee Transactions On Circuits and Systems. 56: 861-864. DOI: 10.1109/Tcsi.2009.2022778  0.328
2009 Sasidhar N, Kook YJ, Takeuchi S, Hamashita K, Takasuka K, Hanumolu PK, Moon UK. A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback Ieee Journal of Solid-State Circuits. 44: 2392-2401. DOI: 10.1109/Jssc.2009.2025408  0.516
2009 Kim MG, Hanumolu PK, Moon UK. A 10 MS/s 11-bit 0.19 mm2 algorithmic ADC with improved clocking scheme Ieee Journal of Solid-State Circuits. 44: 2348-2355. DOI: 10.1109/Jssc.2009.2023158  0.464
2009 Maghari N, Kwon S, Moon UK. 74 dB SNDR multi-loop sturdy-mash delta-sigma modulator using 35 db open-loop opamp gain Ieee Journal of Solid-State Circuits. 44: 2212-2221. DOI: 10.1109/Jssc.2009.2022302  0.803
2009 Lee K, Meng Q, Sugimoto T, Hamashita K, Takasuka K, Takeuchi S, Moon U, Temes GC. A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver Ieee Journal of Solid-State Circuits. 44: 916-927. DOI: 10.1109/Jssc.2008.2012362  0.429
2009 Wu T, Hanumolu PK, Mayaram K, Moon UK. Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers Ieee Journal of Solid-State Circuits. 44: 427-435. DOI: 10.1109/Jssc.2008.2010792  0.421
2009 Musah T, Kwon S, Lakdawala H, Soumyanath K, Moon UK. A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS Proceedings of the Custom Integrated Circuits Conference. 1-4. DOI: 10.1109/CICC.2009.5280909  0.833
2009 Kwon S, Hanumolu PK, Kim SH, Lee SN, You SB, Park HJ, Kim JW, Moon UK. An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing Proceedings of the Custom Integrated Circuits Conference. 171-174. DOI: 10.1109/CICC.2009.5280871  0.401
2009 Gubbins D, Kwon S, Lee B, Hanumolu PK, Moon UK. A continuous-time input pipeline ADC with inherent anti-alias filtering Proceedings of the Custom Integrated Circuits Conference. 275-278. DOI: 10.1109/CICC.2009.5280858  0.3
2009 Maghari N, Temes GC, Moon U. Noise-shaped integrating quantisers in ΔΣ modulators Electronics Letters. 45: 612-613. DOI: 10.1049/El.2009.0744  0.772
2009 Musah T, Moon UK. Correlated level shifting technique with cross-coupled gain-enhancement capacitors Electronics Letters. 45: 672-674. DOI: 10.1049/El.2009.0208  0.785
2009 Weaver S, Hershberg B, Hanumolu PK, Moon UK. A multiplexer-based digital passive linear counter (PLINCO) 2009 16th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2009. 607-610. DOI: 10.1007/S10470-012-9862-3  0.812
2008 Jaussi JE, Balamurugan G, Kennedy J, O'Mahony F, Mansuri M, Mooney R, Casper B, Moon UK. In-situ jitter tolerance measurement technique for serial I/O Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 158-159. DOI: 10.1109/VLSIC.2008.4585993  0.349
2008 Kim MG, Ahn GC, Hanumolu PK, Lee SH, Kim SH, You SB, Kim JW, Temes GC, Moon UK. A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC Ieee Journal of Solid-State Circuits. 43: 1195-1205. DOI: 10.1109/Jssc.2008.920329  0.763
2008 Gregoire BR, Moon UK. An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 db loop gain Ieee Journal of Solid-State Circuits. 43: 2620-2630. DOI: 10.1109/Jssc.2008.2006312  0.524
2008 Hanumolu PK, Wei GY, Moon UK. A wide-tracking range clock and data recovery circuit Ieee Journal of Solid-State Circuits. 43: 425-438. DOI: 10.1109/Jssc.2007.914290  0.472
2008 Hanumolu PK, Kratyuk V, Wei GY, Moon UK. A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter Ieee Journal of Solid-State Circuits. 43: 414-423. DOI: 10.1109/Jssc.2007.914287  0.821
2008 Gregoire BR, Moon UK. An over-60dB true rail-to-rail performance using correlated level shifting and an opamp with 30dB loop gain Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 51. DOI: 10.1109/ISSCC.2008.4523296  0.375
2008 Maghari N, Moon UK. Multi-loop efficient sturdy MASH delta-sigma modulators Proceedings - Ieee International Symposium On Circuits and Systems. 1216-1219. DOI: 10.1109/ISCAS.2008.4541643  0.726
2008 Rajaee O, Moon UK. Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer Proceedings - Ieee International Symposium On Circuits and Systems. 1212-1215. DOI: 10.1109/ISCAS.2008.4541642  0.838
2008 Kurahashi P, Hanumolu PK, Moon UK. A 1V downconversion filter using duty-cycle controlled bandwidth tuning Proceedings of the Custom Integrated Circuits Conference. 707-710. DOI: 10.1109/CICC.2008.4672185  0.807
2008 Gubbins D, Lee B, Hanumolu PK, Moon UK. A continuous-time input pipeline ADC Proceedings of the Custom Integrated Circuits Conference. 169-172. DOI: 10.1109/CICC.2008.4672050  0.4
2008 Maghari N, Kwon S, Moon UK. 74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain Proceedings of the Custom Integrated Circuits Conference. 101-104. DOI: 10.1109/CICC.2008.4672031  0.761
2008 Ahn GC, Kim MG, Hanumolu PK, Moon UK. A 1V 10b 30MSPS switched-RC pipelined ADC Proceedings of the Custom Integrated Circuits Conference. 325-328. DOI: 10.1109/CICC.2007.4405744  0.732
2008 Kook YJ, Li J, Lee B, Moon UK. Low-power and high-speed pipelined ADC using time-aligned CDS technique Proceedings of the Custom Integrated Circuits Conference. 321-324. DOI: 10.1109/CICC.2007.4405743  0.349
2008 Kratyuk V, Hanumolu PK, Mayaram K, Moon UK. A 0.6GHz to 2GHz digital PLL with wide tracking range Proceedings of the Custom Integrated Circuits Conference. 305-308. DOI: 10.1109/CICC.2007.4405739  0.813
2008 Weaver S, Hershberg B, Knierim D, Moon UK. A 6b stochastic flash analog-to-digital converter without calibration or reference ladder Proceedings of 2008 Ieee Asian Solid-State Circuits Conference, a-Sscc 2008. 373-376. DOI: 10.1109/ASSCC.2008.4708805  0.38
2008 Kim MG, Kratyuk V, Hanumolu PK, Ahn GC, Kwon S, Moon UK. An 8mW 10b 50MS/s pipelined ADC using 25dB opamp Proceedings of 2008 Ieee Asian Solid-State Circuits Conference, a-Sscc 2008. 49-52. DOI: 10.1109/ASSCC.2008.4708726  0.832
2008 Maghari N, Temes GC, Moon U. Single-loop ΔΣ modulator with extended dynamic range Electronics Letters. 44: 1452-1453. DOI: 10.1049/El:20082717  0.735
2007 Gregoire BR, Moon UK. A sub 1-V constant Gm-C switched-capacitor current source Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 222-226. DOI: 10.1109/Tcsii.2006.889446  0.427
2007 Kratyuk V, Hanumolu PK, Moon UK, Mayaram K. A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy Ieee Transactions On Circuits and Systems Ii: Express Briefs. 54: 247-251. DOI: 10.1109/Tcsii.2006.889443  0.806
2007 Kurahashi P, Hanumolu PK, Temes GC, Moon UK. Design of low-voltage highly linear switched-R-MOSFET-C filters Ieee Journal of Solid-State Circuits. 42: 1699-1708. DOI: 10.1109/Jssc.2007.900280  0.824
2007 Desikachari R, Steeds M, Huard J, Moon U. An efficient design procedure for high-speed low-power Dual-Modulus CMOS prescalers Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 645-648. DOI: 10.1109/ICECS.2007.4511074  0.318
2007 Rajaee O, Maghari N, Moon UK. Time-shifted CDS enhancement of comparator-based MDAC for pipelined ADC applications Proceedings of the Ieee International Conference On Electronics, Circuits, and Systems. 210-213. DOI: 10.1109/ICECS.2007.4510967  0.783
2007 Wu T, Hanumolu PK, Mayaram K, Moon UK. A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 547-550. DOI: 10.1109/CICC.2007.4405791  0.393
2007 Hanumolu PK, Wei GY, Moon UK, Mayaram K. Digitally-Enhanced Phase-Locking Circuits Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 361-368. DOI: 10.1109/CICC.2007.4405753  0.369
2007 Brownlee M, Hanumolu PK, Moon UK. A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance Proceedings of the Ieee 2007 Custom Integrated Circuits Conference, Cicc 2007. 353-356. DOI: 10.1109/CICC.2007.4405751  0.357
2007 Sasidhar N, Kook YJ, Takeuchi S, Hamashita K, Takasuka K, Hanumolu PK, Moon UK. A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing 2007 Ieee Asian Solid-State Circuits Conference, a-Sscc. 240-243. DOI: 10.1109/ASSCC.2007.4425775  0.427
2007 Carnes J, Ahn GC, Moon UK. A 1V 10b 60MS/s hybrid opamp-reset/switched-RC pipelined ADC 2007 Ieee Asian Solid-State Circuits Conference, a-Sscc. 236-239. DOI: 10.1109/ASSCC.2007.4425774  0.736
2007 Kratyuk V, Hanumolu PK, Moon UK, Mayaram K. Frequency detector for fast frequency lock of digital PLLs Electronics Letters. 43: 13-15. DOI: 10.1049/El:20073292  0.778
2007 Musah T, Gregoire BR, Naviasky E, Moon UK. Parallel correlated double sampling technique for pipelined analogue-to-digital converters Electronics Letters. 43: 1260-1261. DOI: 10.1049/El:20072152  0.797
2007 Wang R, Kim S, Lee S, You S, Kim J, Moon U, Temes GC. A 100-dB gain-corrected delta-sigma audio DAC with headphone driver Analog Integrated Circuits and Signal Processing. 51: 27-31. DOI: 10.1007/S10470-007-9033-0  0.429
2007 Kwon S, Moon UK. A high-speed Delta-Sigma modulator with relaxed DEM timing requirement Proceedings - Ieee International Symposium On Circuits and Systems. 733-736.  0.361
2007 Maghari N, Kwon S, Ternes GC, Moon U. Mixed-order sturdy MASH Δ-∑ modulator Proceedings - Ieee International Symposium On Circuits and Systems. 257-260.  0.749
2006 Wu T, Mayaram K, Moon UK. An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 102-103. DOI: 10.1109/Jssc.2007.892194  0.5
2006 Brownlee M, Hanumolu PK, Mayaram K, Moon UK. A 0.5-GHz to 2.5-GHz PLL with fully differential supply regulated tuning Ieee Journal of Solid-State Circuits. 41: 2720-2727. DOI: 10.1109/Jssc.2006.884194  0.503
2006 Li J, Moon UK, McNeill JA, Coln M, Larivee B. Comments on ""Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC", Ieee Journal of Solid-State Circuits. 41: 1481. DOI: 10.1109/Jssc.2006.875939  0.524
2006 Kurahashi P, Hanumolu PK, Ternes G, Moon UK. A 0.6V highly linear switched-R-MOSFET-C filter Proceedings of the Custom Integrated Circuits Conference. 833-836. DOI: 10.1109/CICC.2006.320841  0.82
2006 Hanumolu PK, Kim MG, Wei GY, Moon UK. A 1.6Gbps digital clock and data recovery circuit Proceedings of the Custom Integrated Circuits Conference. 603-606. DOI: 10.1109/CICC.2006.320829  0.421
2006 Maghari N, Kwon S, Temes GC, Moon U. Sturdy MASH Δ-Σ modulator Electronics Letters. 42: 1269-1270. DOI: 10.1049/El:20062718  0.748
2006 Hanumolu PK, Wei GY, Moon UK. A wide tracking range 0.2-4Gbps clock and data recovery circuit Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 71-72.  0.402
2006 Kim MG, Hanumolu PK, Moon UK. A 10MS/s 11-b 0.19mm2 algorithmic ADC with improved clocking Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 49-50.  0.362
2006 Brownlee M, Hanumolu PK, Mayaram K, Moon UK. A 0.5 to 2.5GHz PLL with fully differential supply-regulated tuning Digest of Technical Papers - Ieee International Solid-State Circuits Conference.  0.394
2006 Talebbeydokhti N, Hanumolu PK, Kurahashi P, Moon UK. Constant transconductance bias circuit with an on-chip resistor Proceedings - Ieee International Symposium On Circuits and Systems. 2857-2860.  0.81
2006 Hanumolu PK, Kratyuk V, Wei GY, Moon UK. A sub-picosecond resolution 0.5-1.5GHz digital-to-phase converter Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 75-76.  0.821
2005 Pulincherry A, Hufford M, Naviasky E, Moon UK. A time-delay jitter-insensitive continuous-time bandpass ΔΣ modulator architecture Ieee Transactions On Circuits and Systems Ii: Express Briefs. 52: 680-684. DOI: 10.1109/Tcsii.2005.850746  0.441
2005 Greenley B, Veith R, Chang D, Moon U. A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area Ieee Transactions On Circuits and Systems Ii-Express Briefs. 52: 246-250. DOI: 10.1109/Tcsii.2005.843595  0.619
2005 Chang DY, Ahn GC, Moon UK. Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters Ieee Transactions On Circuits and Systems I: Regular Papers. 52: 1-12. DOI: 10.1109/Tcsi.2004.839532  0.786
2005 Ahn GC, Chang DY, Brown ME, Ozaki N, Youra H, Yamamura K, Hamashita K, Takasuka K, Temes GC, Moon UK. A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators Ieee Journal of Solid-State Circuits. 40: 2398-2406. DOI: 10.1109/Jssc.2005.856286  0.774
2005 Vemulapalli G, Hanumolu PK, Kook YJ, Moon UK. A 0.8-V accurately tuned linear continuous-time filter Ieee Journal of Solid-State Circuits. 40: 1972-1977. DOI: 10.1109/Jssc.2005.848170  0.487
2005 Li J, Ahn GC, Chang DY, Moon UK. A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR Ieee Journal of Solid-State Circuits. 40: 960-969. DOI: 10.1109/Jssc.2004.842866  0.813
2005 Rao A, McIntyre W, Moon U, Temes GC. Noise-shaping techniques applied to switched-capacitor voltage regulators Ieee Journal of Solid-State Circuits. 40: 422-429. DOI: 10.1109/Jssc.2004.840986  0.485
2005 Kratyuk V, Vytyaz I, Moon UK, Mayaram K. Analysis of supply and ground noise sensitivity in ring and LC oscillators Proceedings - Ieee International Symposium On Circuits and Systems. 5986-5989. DOI: 10.1109/ISCAS.2005.1466003  0.802
2005 Kratyuk V, Hanumolu PK, Moon UK, Mayaram K. A low spur fractional-N frequency synthesizer architecture Proceedings - Ieee International Symposium On Circuits and Systems. 2807-2810. DOI: 10.1109/ISCAS.2005.1465210  0.804
2004 Yoo S, Park J, Lee S, Moon U. A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching Ieee Transactions On Circuits and Systems Ii-Express Briefs. 51: 269-275. DOI: 10.1109/Tcsii.2004.827555  0.56
2004 Myers C, Greenley B, Thomas D, Moon U. Continuous-time filter design optimized for reduced die area Ieee Transactions On Circuits and Systems Ii-Express Briefs. 51: 105-110. DOI: 10.1109/Tcsii.2003.822425  0.371
2004 Chang D, Li J, Moon U. Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs Ieee Transactions On Circuits and Systems. 51: 2133-2140. DOI: 10.1109/Tcsi.2004.836863  0.595
2004 Hanumolu PK, Brownlee M, Mayaram K, Moon UK. Analysis of charge-pump phase-locked loops Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 1665-1674. DOI: 10.1109/Tcsi.2004.834516  0.372
2004 Moon UK, Huang G. CMOS implementation of nonlinear spectral-line timing recovery in digital data-communication systems Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 298-308. DOI: 10.1109/Tcsi.2003.822395  0.47
2004 Li J, Moon UK. A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique Ieee Journal of Solid-State Circuits. 39: 1468-1476. DOI: 10.1109/Jssc.2004.829378  0.492
2004 Vemulapalli G, Hanumolu PK, Moon UK. A 0.8V accurately-tuned continuous-time filter Proceedings of the Custom Integrated Circuits Conference. 45-48.  0.319
2004 Xiao S, Silva J, Moon UK, Temes G. A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.318
2004 Silva J, Moon UK, Temes GC. Low-distortion delta-sigma topologies for MASH architectures Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.34
2004 Kim MG, Ahn GC, Moon UK. An improved algorithmic ADC clocking scheme Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.663
2004 Wang X, Guo Y, Moon UK, Temes GC. Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs Proceedings of the Custom Integrated Circuits Conference. 523-526.  0.379
2004 Li J, Ahn GC, Chang DY, Moon UK. 0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 436-439.  0.76
2003 Hanumolu PK, Casper B, Mooney R, Wei GY, Moon UK. Analysis of PLL Clock Jitter in High-Speed Serial Links Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 879-886. DOI: 10.1109/Tcsii.2003.819121  0.401
2003 Li J, Moon UK. Background calibration techniques for multistage pipelined ADCs with digital redundancy Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 50: 531-538. DOI: 10.1109/Tcsii.2003.816921  0.666
2003 Greenley BR, Veith RL, Chang DY, Moon UK. A 1.4V 10b CMOS DC DAC in 0.01mm2 Proceedings - Ieee International Soc Conference, Socc 2003. 237-238. DOI: 10.1109/SOC.2003.1241500  0.34
2003 Chang DY, Moon UK. A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique Ieee Journal of Solid-State Circuits. 38: 1401-1404. DOI: 10.1109/Jssc.2003.814427  0.65
2003 Li J, Moon UK. A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique Proceedings of the Custom Integrated Circuits Conference. 413-416.  0.389
2003 Chang DY, Ahn GC, Moon UK. A 0.9V 9mW 1MSPS digitally calibrated ADC with 75dB SFDR Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 67-70.  0.762
2002 Kajita T, Moon U, Temes GC. A two-chip interface for a MEMS accelerometer Ieee Transactions On Instrumentation and Measurement. 51: 853-858. DOI: 10.1109/Tim.2002.803508  0.487
2002 Ou Y, Barton N, Fetche R, Seshan N, Fiez T, Moon U, Mayaram K. Phase noise simulation and estimation methods: a comparative study Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 49: 635-638. DOI: 10.1109/Tcsii.2002.806739  0.368
2002 Keskin M, Moon U, Temes GC. A 1-V 10-MHz clock-rate 13-bit CMOS /spl Delta//spl Sigma/ modulator using unity-gain-reset op amps Ieee Journal of Solid-State Circuits. 37: 817-824. DOI: 10.1109/Jssc.2002.1015678  0.541
2002 Kajita T, Moon UK, Temes GC. A noise-shaping accelerometer interface circuit for two-chip implementation Vlsi Design. 14: 355-361. DOI: 10.1080/10655140290011168  0.506
2002 Keskin M, Moon UK, Temes GC. Direct-charge-transfer pseudo-N-path SC circuit insensitive to the element mismatch and opamp nonidealities Analog Integrated Circuits and Signal Processing. 30: 243-247. DOI: 10.1023/A:1014484518543  0.379
2002 Chang DY, Moon UK. Radix-based digital calibration technique for multi-stage ADC Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.32
2002 Rao A, McIntyre W, Moon U, Temes G. A noise-shaped switched-capacitor DC-DC voltage regulator European Solid-State Circuits Conference. 375-378.  0.364
2002 Chang DY, Wu L, Moon UK. Low-voltage pipelined ADC using opamp-reset switching technique Proceedings of the Custom Integrated Circuits Conference. 461-464.  0.399
2002 Rao A, McIntyre W, Parry J, Moon U, Temes G. Buck-boost switched-capacitor dc-dc voltage regulator using delta-sigma control loop Proceedings - Ieee International Symposium On Circuits and Systems. 4.  0.305
2002 Yoo SM, Pj TJ, Moon JW, Lee SH, Moon UK. A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR Proceedings of the Custom Integrated Circuits Conference. 441-444.  0.336
2001 Greenley BR, Moon UK, Veith R. A 1.8 v CMOS DAC cell with ultra high gain op-amp in 0.0143 mm2 Iscas 2001 - 2001 Ieee International Symposium On Circuits and Systems, Conference Proceedings. 1: 412-415. DOI: 10.1109/ISCAS.2001.921880  0.426
2001 Keskin M, Moon UK, Temes GC. Low-voltage low-sensitivity switched-capacitor bandpass ΔΣ modulator Proceedings - Ieee International Symposium On Circuits and Systems. 1: 348-351. DOI: 10.1109/ISCAS.2001.921864  0.372
2001 Silva J, Moon U, Steensgaard J, Temes GC. Wideband low-distortion delta-sigma ADC topology Electronics Letters. 37: 737-738. DOI: 10.1049/El:20010542  0.405
2001 Chang D, Moon U. 1V input sampling circuit with improved linearity Electronics Letters. 37: 479-481. DOI: 10.1049/El:20010333  0.469
2001 Wang X, Kiss P, Moon U, Steensgaard J, Temes GC. Digital estimation and correction of DAC errors in multibit Δ∑ ADCs Electronics Letters. 37: 414-415. DOI: 10.1049/El:20010304  0.344
2001 Keskin M, Moon UK, Temes GC. Switched-capacitor resonator structure with improved performance Electronics Letters. 37: 212-213. DOI: 10.1049/El:20010158  0.398
2001 Kiss P, Moon U, Steensgaard J, Stonick JT, Temes GC. High-speed ΔΣ ADC with error correction Electronics Letters. 37: 76-77. DOI: 10.1049/El:20010069  0.383
2001 Keskin M, Moon UK, Temes GC. A 1-V, 10-MHz clock-rate, 13-bit CMOS ΔΣ modulator using unity-gain-reset opamps European Solid-State Circuits Conference. 534-537.  0.447
2000 Moon U. Correction to "CMOS high-frequency switched-capacitor filters for telecommunication applications" Ieee Journal of Solid-State Circuits. 35: 920-920. DOI: 10.1109/Jssc.2000.845198  0.39
2000 Kiss P, Silva J, Wiesbauer A, Sun T, Moon U, Stonick JT, Temes GC. Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 47: 629-638. DOI: 10.1109/82.850422  0.439
2000 Wilson WB, Moon UK, Lakshmikumar KR, Dai L. CMOS self-calibrating frequency synthesizer Ieee Journal of Solid-State Circuits. 35: 1437-1444. DOI: 10.1109/4.871320  0.43
2000 Moon UK. CMOS high-frequency switched-capacitor filters for telecommunication applications Ieee Journal of Solid-State Circuits. 35: 212-220. DOI: 10.1109/4.823446  0.511
2000 Lehne M, Stonick JT, Moon U. Adaptive offset cancellation mixer for direct conversion receivers in 2.4 GHz CMOS Proceedings - Ieee International Symposium On Circuits and Systems. 1.  0.403
2000 Wu L, Keskin M, Moon U, Temes G. Efficient common-mode feedback circuits for pseudo-differential switched-capacitor stages Proceedings - Ieee International Symposium On Circuits and Systems. 5.  0.334
1999 Moon U, Temes GC, Steensgaard J. Digital techniques for improving the accuracy of data converters Ieee Communications Magazine. 37: 136-143. DOI: 10.1109/35.795604  0.41
1999 Moon U, Silva J, Steensgaard J, Temes GC. Switched-capacitor DAC with analogue mismatch correction Electronics Letters. 35: 1903-1904. DOI: 10.1049/El:19991288  0.417
1999 Bidari E, Keskin M, Maloberti F, Moon U, Steensgaard J, Temes GC. Low-voltage switched-capacitor circuits Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.32
1998 Steensgaard J, Moon U, Temes GC. Mismatch-shaping switching for two-capacitor DAC Electronics Letters. 34: 1633-1634. DOI: 10.1049/El:19981121  0.435
1998 Steensgaard J, Moon U, Temes GC. Mismatch-shaping switching for two-capacitor DAC Electronics Letters. 34: 1633-1634.  0.323
1997 Moon UK, Song BS. Background digital calibration techniques for pipelined ADC's Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 44: 102-109. DOI: 10.1109/82.554434  0.587
1993 Moon UK, Song BS. Design of a Low-Distortion 22-kHz Fifth-Order Bessel Filter Ieee Journal of Solid-State Circuits. 28: 1254-1264. DOI: 10.1109/4.261999  0.323
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