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Rajesh Inti, Ph.D. - Publications

Affiliations: 
2011 Oregon State University, Corvallis, OR 
Area:
Electronics and Electrical Engineering
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24 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2019 Shekhar S, Inti R, Jaussi J, Hsueh T, Casper BK. A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR Ieee Journal of Solid-State Circuits. 54: 1669-1681. DOI: 10.1109/Jssc.2019.2894367  0.552
2015 Shekhar S, Inti R, Jaussi J, Hsueh TC, Casper B. A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2015: C350-C351. DOI: 10.1109/VLSIC.2015.7231319  0.445
2014 Musah T, Jaussi J, Balamurugan G, Hyvonen S, Hsueh TC, Keskin G, Shekhar S, Kennedy J, Sen S, Inti R, Mansuri M, Leddige M, Horine B, Roberts C, Mooney R, et al. A 4-32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS Ieee Journal of Solid-State Circuits. 49: 3079-3090. DOI: 10.1109/Jssc.2014.2348556  0.549
2014 Shu G, Saxena S, Choi WS, Talegaonkar M, Inti R, Elshazly A, Young B, Hanumolu PK. A reference-less clock and data recovery circuit using phase-rotating phase-locked loop Ieee Journal of Solid-State Circuits. 49: 1036-1047. DOI: 10.1109/Jssc.2013.2296152  0.818
2013 Elshazly A, Inti R, Young B, Hanumolu PK. Clock multiplication techniques using digital multiplying delay-locked loops Ieee Journal of Solid-State Circuits. 48: 1416-1428. DOI: 10.1109/Jssc.2013.2254552  0.83
2013 Shu G, Saxena S, Choi WS, Talegaonkar M, Inti R, Elshazly A, Young B, Hanumolu PK. A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR Ieee Symposium On Vlsi Circuits, Digest of Technical Papers.  0.784
2012 Elshazly A, Inti R, Talegaonkar M, Hanumolu PK. A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 188-189. DOI: 10.1109/VLSIC.2012.6243853  0.797
2012 Khan Q, Elshazly A, Rao S, Inti R, Hanumolu PK. A 900mA 93% efficient 50μA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 182-183. DOI: 10.1109/VLSIC.2012.6243850  0.745
2012 Toifl T, Ruegg M, Inti R, Menolfi C, Brandli M, Kossel M, Buchmann P, Francese PA, Morf T. A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 102-103. DOI: 10.1109/VLSIC.2012.6243810  0.429
2012 Reddy K, Rao S, Inti R, Young B, Elshazly A, Talegaonkar M, Hanumolu PK. A 16-mW 78-dB SNDR 10-MHz BW CT Δσ ADC Using Residue-Cancelling VCO-Based Quantizer Ieee Journal of Solid-State Circuits. 47: 2916-2927. DOI: 10.1109/Jssc.2012.2218062  0.786
2012 Elshazly A, Inti R, Young B, Hanumolu PK. A 1.5GHz 890μW digital MDLL with 400fs rms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 242-243. DOI: 10.1109/ISSCC.2012.6176993  0.814
2012 Reddy K, Rao S, Inti R, Young B, Elshazly A, Talegaonkar M, Hanumolu PK. A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 55: 152-153. DOI: 10.1109/ISSCC.2012.6176955  0.817
2011 Yin W, Inti R, Elshazly A, Talegaonkar M, Young B, Hanumolu PK. A TDC-less 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery Ieee Journal of Solid-State Circuits. 46: 3163-3173. DOI: 10.1109/JSSC.2011.2168873  0.799
2011 Inti R, Yin W, Elshazly A, Sasidhar N, Hanumolu PK. A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance Ieee Journal of Solid-State Circuits. 46: 3150-3162. DOI: 10.1109/JSSC.2011.2168872  0.794
2011 Elshazly A, Inti R, Yin W, Young B, Hanumolu PK. A 0.4-to-3 GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration Ieee Journal of Solid-State Circuits. 46: 2759-2771. DOI: 10.1109/Jssc.2011.2162912  0.831
2011 Yin W, Inti R, Elshazly A, Young B, Hanumolu PK. A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking Ieee Journal of Solid-State Circuits. 46: 1870-1880. DOI: 10.1109/Jssc.2011.2157259  0.835
2011 Yin W, Inti R, Elshazly A, Hanumolu PK. A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 440-441. DOI: 10.1109/ISSCC.2011.5746388  0.756
2011 Inti R, Yin W, Elshazly A, Sasidhar N, Hanumolu PK. A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 438-439. DOI: 10.1109/ISSCC.2011.5746387  0.768
2011 Inti R, Elshazly A, Young B, Yin W, Kossel M, Toifl T, Hanumolu PK. A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 152-153. DOI: 10.1109/ISSCC.2011.5746260  0.754
2011 Elshazly A, Inti R, Yin W, Young B, Hanumolu PK. A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 92-93. DOI: 10.1109/ISSCC.2011.5746233  0.82
2011 Talegaonkar M, Inti R, Hanumolu PK. Digital clock and data recovery circuit design: Challenges and tradeoffs Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2011.6055346  0.664
2010 Venkatram H, Inti R, Moon UK. Least Mean Square calibration method for VCO non-linearity Proceedings of the International Conference On Microelectronics, Icm. 1-4. DOI: 10.1109/ICM.2010.5696115  0.407
2010 Yin W, Inti R, Hanumolu PK. A 1.6mW 1.6ps-rms-Jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617611  0.719
2009 Sasidhar N, Inti R, Hanumolu PK. Low-noise self-referenced CMOS oscillator Electronics Letters. 45: 920-921. DOI: 10.1049/El.2009.1342  0.738
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