Shantanu Dutt
Affiliations: | University of Illinois at Chicago, Chicago, IL, United States |
Area:
Computer ScienceGoogle:
"Shantanu Dutt"
BETA: Related publications
See more...
Publications
|
You can help our author matching system! If you notice any publications incorrectly attributed to this author, please sign in and mark matches as correct or incorrect. |
| Ren H, Dutt S. (2013) Fast and near-optimal timing-driven cell sizing under cell area and leakage power constraints using a simplified discrete network flow algorithm Vlsi Design. 2013 |
| Dutt S, Ren H. (2011) Discretized network flow techniques for timing and wire-length driven incremental placement with white-space satisfaction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1277-1290 |
| Ren H, Dutt S. (2011) A provably high-probability white-space satisfaction algorithm with good performance for standard-cell detailed placement Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1291-1304 |
| Ren H, Dutt S. (2011) Effective power optimization under timing and voltage-island constraints via simultaneous VDD, Vth assignments, gate sizing, and placement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 746-759 |
| Dutt S, Li L. (2009) Trust-based design and check of FPGA circuits using two-level randomized ECC structures Acm Transactions On Reconfigurable Technology and Systems. 2 |
| Dutt S, Verma V, Suthar V. (2008) Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 309-326 |
| Ren H, Dutt S. (2008) Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closuret Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 93-100 |
| Mahapatra NR, Dutt S. (2007) An efficient delay-optimal distributed termination detection algorithm Journal of Parallel and Distributed Computing. 67: 1047-1066 |
| Dutt S, Deng W. (2002) Cluster-aware iterative improvement techniques for partitioning large VLSI circuits Acm Transactions On Design Automation of Electronic Systems. 7: 91-121 |
| Verma V, Dutt S. (2001) A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 144-151 |