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Ganesh S. Dasika, Ph.D. - Publications

Affiliations: 
2011 University of Michigan, Ann Arbor, Ann Arbor, MI 
Area:
Computer Engineering, Computer Science, Electronics and Electrical Engineering
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8 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Das S, Dasika GS, Shivashankar K, Bull D. A 1 GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation Ieee Transactions On Circuits and Systems I: Regular Papers. 61: 2290-2298. DOI: 10.1109/Tcsi.2014.2333332  0.47
2012 Sethia A, Dasika G, Mudge T, Mahlke S. A customized processor for energy efficient scientific computing Ieee Transactions On Computers. 61: 1711-1723. DOI: 10.1109/Tc.2012.144  0.709
2011 Bull D, Das S, Shivashankar K, Dasika GS, Flautner K, Blaauw D. Correction to “A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation” Ieee Journal of Solid-State Circuits. 46: 705-705. DOI: 10.1109/Jssc.2011.2111230  0.421
2011 Bull D, Das S, Shivashankar K, Dasika GS, Flautner K, Blaauw D. A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation Ieee Journal of Solid-State Circuits. 46: 18-31. DOI: 10.1109/JSSC.2010.2079410  0.344
2005 Ravindran RA, Senger RM, Marsman ED, Dasika GS, Guthaus MR, Mahlke SA, Brown RB. Partitioning variables across register windows to reduce spill code in a low-power processor Ieee Transactions On Computers. 54: 998-1012. DOI: 10.1109/Tc.2005.132  0.677
2005 Marsman ED, Senger RM, McCorquodale MS, Guthaus MR, Ravindran RA, Dasika GS, Mahlke SA, Brown RB. A 16-bit low-power microcontroller with monolithic MEMS-LC clocking Proceedings - Ieee International Symposium On Circuits and Systems. 624-627. DOI: 10.1109/ISCAS.2005.1464665  0.691
2005 Ravindran RA, Nagarkar PD, Dasika GS, Marsman ED, Senger RM, Mahlke SA, Brown RB. Compiler managed dynamic instruction placement in a low-power code cache Proceedings of the 2005 International Symposium On Code Generation and Optimization, Cgo 2005. 2005: 179-190. DOI: 10.1109/CGO.2005.13  0.672
2003 Ravindran RA, Senger RM, Marsman ED, Dasika GS, Guthaus MR, Mahlke SA, Brown RB. Increasing the number of effective registers in a low-power processor using a windowed register file Cases 2003: International Conference On Compilers, Architecture, and Synthesis For Embedded Systems. 125-136.  0.69
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