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Anup P. Jose, Ph.D. - Publications

Affiliations: 
2006 Columbia University, New York, NY 
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12 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Frans Y, Carey D, Erett M, Amir-Aslanzadeh H, Fang WY, Turker D, Jose AP, Bekele A, Im J, Upadhyaya P, Wu ZD, Hsieh KCH, Savoj J, Chang K. A 0.5-16.3 Gb/s fully adaptive flexible-reach transceiver for FPGA in 20 nm CMOS Ieee Journal of Solid-State Circuits. 50: 1932-1944. DOI: 10.1109/Jssc.2015.2413849  0.477
2014 Savoj J, Aslanzadeh H, Carey D, Erett M, Fang W, Frans Y, Hsieh K, Im J, Jose A, Turker D, Upadhyaya P, Wu D, Chang K. Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS Proceedings of the Ieee 2014 Custom Integrated Circuits Conference, Cicc 2014. DOI: 10.1109/CICC.2014.6945980  0.349
2013 Savoj J, Hsieh KCH, An FT, Gong J, Im J, Jiang X, Jose AP, Kireev V, Lim SW, Roldan A, Turker DZ, Upadhyaya P, Wu D, Chang K. A low-power 0.5-6.6 Gb/s wireline transceiver embedded in low-cost 28 nm FPGAs Ieee Journal of Solid-State Circuits. 48: 2581-2594. DOI: 10.1109/Jssc.2013.2274824  0.494
2010 Jenkins KA, Xu Z, Jose AP, Shepard KL. On-chip circuit technique for measuring jitter and skew with picosecond resolution Lecture Notes in Electrical Engineering. 2021: 203-217. DOI: 10.1007/978-90-481-9379-0_15  0.595
2008 Jenkins KA, Jose AP, Xu Z, Shepard KL. On-chip circuit for measuring jitter and skew with picosecond resolution Proceedings - 2008 Ieee International Conference On Integrated Circuit Design and Technology, Icicdt. 257-260. DOI: 10.1109/ICICDT.2008.4567290  0.554
2007 Jose AP, Shepard KL. Distributed loss-compensation techniques for energy-efficient low-latency on-chip communication Ieee Journal of Solid-State Circuits. 42: 1415-1424. DOI: 10.1109/Jssc.2007.897165  0.594
2006 Jose AP, Patounakis G, Shepard KL. Pulsed current-mode signaling for nearly speed-of-light intrachip communication Ieee Journal of Solid-State Circuits. 41: 772-780. DOI: 10.1109/Jssc.2006.870922  0.64
2006 Jose AP, Shepard KL. Distributed loss compensation for low-latency on-chip interconnects Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 392+379.  0.547
2005 Jose AP, Jenkins KA, Reynolds SK. On-chip spectrum analyzer for analog built-in self test Proceedings of the Ieee Vlsi Test Symposium. 131-136. DOI: 10.1109/VTS.2005.63  0.356
2005 Jose AP, Patounakis G, Shepard KL. Near speed-of-light on-chip interconnects using pulsed current-mode signalling Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 2005: 108-111. DOI: 10.1109/VLSIC.2005.1469345  0.652
2005 Jenkins KA, Jose AP, Heidel DF. An on-chip jitter measurement circuit with sub-picosecond resolution Proceedings of Esscirc 2005: 31st European Solid-State Circuits Conference. 157-160. DOI: 10.1109/ESSCIR.2005.1541583  0.38
2003 Li YW, Patounakis G, Jose A, Shepard KL, Nowick SM. Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications Proceedings - International Symposium On Asynchronous Circuits and Systems. 216-225. DOI: 10.1109/ASYNC.2003.1199181  0.596
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