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Suresh Sitaraman - Publications

Affiliations: 
Georgia Institute of Technology, Atlanta, GA 
Area:
Mechanical Engineering, Computer Science
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58 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Green C, Kottke P, Han X, Woodrum C, Sarvey T, Asrar P, Zhang X, Joshi Y, Fedorov A, Sitaraman S, Bakir M. A review of two-phase forced cooling in three-dimensional stacked electronics: Technology integration Journal of Electronic Packaging, Transactions of the Asme. 137. DOI: 10.1115/1.4031481  0.342
2013 Raghavan S, Schmadlak I, Leal G, Sitaraman S. Chip-package co-design: Effect of substrate warpage on BEOL reliability Asme International Mechanical Engineering Congress and Exposition, Proceedings (Imece). 10. DOI: 10.1115/IMECE2013-65877  0.307
2013 Okereke R, Sitaraman SK. Three-path electroplated copper compliant interconnects - Fabrication and modeling studies Proceedings - Electronic Components and Technology Conference. 129-135. DOI: 10.1109/ECTC.2013.6575562  0.332
2013 Liu X, Chen Q, Sundaram V, Tummala RR, Sitaraman SK. Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test Microelectronics Reliability. 53: 70-78. DOI: 10.1016/J.Microrel.2012.06.140  0.301
2010 Okereke R, Kacker K, Sitaraman SK. Parallel-path compliant structures as electrical interconnects Asme International Mechanical Engineering Congress and Exposition, Proceedings (Imece). 4: 479-486. DOI: 10.1115/IMECE2010-38376  0.73
2010 Liu X, Zheng J, Sitaraman SK. Hygro-Thermo-Mechanical Reliability Assessment of a Thermal Interface Material for a Ball Grid Array Package Assembly Journal of Electronic Packaging. 132. DOI: 10.1115/1.4001746  0.583
2010 Zheng J, Ostrowicki G, Sitaraman SK. Cyclic Magnetic Actuation for Potential Characterization of Interfacial Fatigue Fracture Ieee Transactions On Components and Packaging Technologies. 33: 648-654. DOI: 10.1109/Tcapt.2010.2058113  0.57
2010 Tunga K, Sitaraman SK. Laser moiré interferometry for fatigue life prediction of lead-free solders Microelectronics Reliability. 50: 2026-2036. DOI: 10.1016/J.Microrel.2010.05.005  0.766
2010 Kim I, Peak RS, Sitaraman SK. ROM: A reliability knowledge representation for collaborative system design Engineering With Computers. 26: 11-33. DOI: 10.1007/S00366-009-0135-4  0.514
2009 Kacker K, Sitaraman SK. Reliability assessment and failure analysis of G-Helix, a free-standing compliant off-chip interconnect Journal of Microelectronics and Electronic Packaging. 6: 59-65. DOI: 10.4071/1551-4897-6.1.59  0.769
2009 Zheng J, Modi M, Ginga N, Sitaraman S. Silicon and nanoscale metal interface characterization using stress-engineered superlayer test methods Ieee Transactions On Components and Packaging Technologies. 32: 333-338. DOI: 10.1109/Tcapt.2009.2021699  0.767
2009 Kacker K, Sitaraman SK. Electrical/mechanical modeling, reliability assessment, and fabrication of FlexConnects: A MEMS-based compliant chip-to-substrate interconnect Journal of Microelectromechanical Systems. 18: 322-331. DOI: 10.1109/Jmems.2008.2011117  0.776
2008 Kim I, Pucha RV, Peak RS, Sitaraman SK. Development of Reliability Allocation and Assessment Algorithms for Designing Multilevel Microelectronic Systems Journal of Microelectronics and Electronic Packaging. 5: 12-25. DOI: 10.4071/1551-4897-5.1.12  0.497
2008 Tunga K, Sitaraman SK. Microstructure evolution based acceleration factor determination for SnAgCu solder joints during thermal cycling International Journal of Materials and Structural Integrity. 2: 173-192. DOI: 10.1504/Ijmsi.2008.018906  0.77
2008 Kacker K, Sitaraman SK. Design and fabrication of flexconnects: A cost-effective implementation of compliant ship-to-substrate interconnects Ieee Transactions On Components and Packaging Technologies. 31: 816-823. DOI: 10.1109/Tcapt.2008.2001199  0.77
2008 Hegde SG, Sitaraman SK. Thermal aging reliability of package-level polymer optical waveguides Ieee Transactions On Advanced Packaging. 31: 410-416. DOI: 10.1109/Tadvp.2008.920653  0.556
2008 Tunga KR, Sitaraman SK. Using carrier fringes to study the high temperature deformation behavior of a BGA package under extended dwell times Proceedings of the Society For Experimental Mechanics, Inc.. 65: 355-365. DOI: 10.1007/S11340-007-9114-0  0.751
2008 Zeng S, Peak RS, Xiao A, Sitaraman S. ZAP: A knowledge-based FEA modeling method for highly coupled variable topology multi-body problems Engineering With Computers. 24: 359-381. DOI: 10.1007/S00366-007-0086-6  0.484
2007 Kacker K, Sokol T, Yun W, Swaminathan M, Sitaraman SK. A heterogeneous array of off-chip interconnects for optimum mechanical and electrical performance Journal of Electronic Packaging, Transactions of the Asme. 129: 460-468. DOI: 10.1115/1.2804096  0.793
2007 Tunga K, Sitaraman SK. An expedient experimental technique for the determination of thermal cycling fatigue life for BGA package solder balls Journal of Electronic Packaging, Transactions of the Asme. 129: 427-433. DOI: 10.1115/1.2804091  0.775
2007 Kacker K, Sokol T, Sitaraman SK. FlexConnects: A cost-effective implementation of compliant chip-to-substrate interconnects Proceedings - Electronic Components and Technology Conference. 1678-1684. DOI: 10.1109/ECTC.2007.374020  0.741
2007 Hegde SG, Sitaraman SK. Stress-induced birefringence in siloxane polymer waveguides Applied Physics Letters. 91. DOI: 10.1063/1.2773753  0.573
2007 Zheng J, Sitaraman SK. Fixtureless superlayer-driven delamination test for nanoscale thin-film interfaces Thin Solid Films. 515: 4709-4716. DOI: 10.1016/J.Tsf.2006.11.065  0.543
2007 Hegde SG, Liu F, Chang GK, Sitaraman SK. Optical loss changes in siloxane polymer waveguides during thermal curing Journal of Applied Polymer Science. 106: 2320-2327. DOI: 10.1002/App.26945  0.525
2006 Perkins A, Tunga K, Sitaraman S. Acceleration factor to relate thermal cycles to power cycles for ceramic ball grid area array packages Journal of Microelectronics and Electronic Packaging. 3: 177-193. DOI: 10.4071/1551-4897-3.4.177  0.78
2005 Mahalingam S, Tonapi S, Sitaraman SK. The characterization of underfill-passivation interface under monotonic and fatigue loading and ITS application to flip chip reliability prediction American Society of Mechanical Engineers, Electronic and Photonic Packaging, Epp. 5: 219-224. DOI: 10.1115/IMECE2005-83029  0.575
2005 Mahalingam S, Tonapi S, Sitaraman SK. A fracture mechanics analysis of underfill delamination in flip chip packages Proceedings of the Asme/Pacific Rim Technical Conference and Exhibition On Integration and Packaging of Mems, Nems, and Electronic Systems: Advances in Electronic Packaging 2005. 1341-1346.  0.545
2004 Klein KM, Sitaraman SK. Compliant stress-engineered interconnects for-next generation packaging American Society of Mechanical Engineers, Electronic and Photonic Packaging, Epp. 4: 219-226. DOI: 10.1115/IMECE2004-61990  0.328
2004 Modi M, Sitaraman SK. Interfacial fracture toughness measurement of a Ti/Si interface Journal of Electronic Packaging, Transactions of the Asme. 126: 301-307. DOI: 10.1115/1.1772410  0.702
2004 Pucha RV, Tunga K, Pyland J, Sitaraman SK. Accelerated Thermal Cycling Guidelines for Electronic Packages in Military Avionics Thermal Environment Journal of Electronic Packaging. 126: 256-264. DOI: 10.1115/1.1756150  0.774
2004 Zhu Q, Ma L, Sitaraman SK. Development of G-Helix structure as off-chip interconnect Journal of Electronic Packaging, Transactions of the Asme. 126: 237-246. DOI: 10.1115/1.1756148  0.552
2004 Tummala RR, Swaminathan M, Tentzeris MM, Laskar J, Chang G, Sitaraman S, Keezer D, Guidotti D, Huang Z, Lim K, Wan L, Bhattacharya SK, Sundaram V, Liu F, Raj PM. The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade Ieee Transactions On Advanced Packaging. 27: 250-267. DOI: 10.1109/Tadvp.2004.830353  0.349
2004 Hegde S, Pucha RV, Sitaraman SK. Enhanced reliability of High-Density Wiring (HDW) substrates through new base substrate and dielectric materials Journal of Materials Science: Materials in Electronics. 15: 287-296. DOI: 10.1023/B:Jmse.0000024228.46348.1D  0.636
2004 Modi MB, Sitaraman SK. Single-sample decohesion test: Mechanics and implementataion International Journal of Fracture. 129: 1-20. DOI: 10.1023/B:Frac.0000038907.94272.E5  0.7
2004 Modi MB, Sitaraman SK. Interfacial fracture toughness measurement for thin film interfaces Engineering Fracture Mechanics. 71: 1219-1234. DOI: 10.1016/S0013-7944(03)00210-8  0.706
2003 Ma L, Zhu Q, Sitaraman SK. Contact reliability of innovative compliant interconnects for next generation electronic packaging American Society of Mechanical Engineers, Electronic and Photonic Packaging, Epp. 3: 9-17. DOI: 10.1115/IMECE2003-41753  0.301
2003 Zhu Q, Ma L, Sitaraman SK. β-Helix: A Lithography-Based Compliant Off-Chip Interconnect Ieee Transactions On Components and Packaging Technologies. 26: 582-590. DOI: 10.1109/Tcapt.2003.817650  0.526
2003 Xie W, Sitaraman SK. Investigation of interfacial delamination of a copper-epoxy interface under monotonic and cyclic loading: Experimental characterization Ieee Transactions On Advanced Packaging. 26: 447-452. DOI: 10.1109/Tadvp.2003.821091  0.507
2003 Xie W, Sitaraman SK. Investigation of interfacial delamination of a copper-epoxy interface under monotonic and cyclic loading: Modeling and evaluation Ieee Transactions On Advanced Packaging. 26: 441-446. DOI: 10.1109/Tadvp.2003.821087  0.498
2003 Zhu Q, Ma L, Sitaraman SK. Design Optimization of One-Turn Helix: A Novel Compliant Off-Chip Interconnect Ieee Transactions On Advanced Packaging. 26: 106-112. DOI: 10.1109/Tadvp.2003.817343  0.577
2003 Modi MB, Sitaraman SK. Single-substrate decohesion test (SSDT) for interfacial fracture toughness measurement Proceedings of 5th Electronics Packaging Technology Conference, Eptc 2003. 456-461. DOI: 10.1109/EPTC.2003.1271565  0.689
2003 Xie W, Sitaraman SK. An experimental technique to determine critical stress intensity factors for delamination initiation Engineering Fracture Mechanics. 70: 1193-1201. DOI: 10.1016/S0013-7944(02)00090-5  0.5
2003 Perkins A, Sitaraman SK. Thermo-mechanical failure comparison and evaluation of CCGA and CBGA electronic packages Proceedings - Electronic Components and Technology Conference. 422-430.  0.309
2003 Modi MB, Sitaraman SK. Measurement of the mode mix dependent interfacial fracture toughness for a Ti/Si interface using a modified decohesion test Advances in Electronic Packaging. 1: 559-573.  0.695
2002 Hegde S, Pucha RV, Sitaraman SK. Enhanced reliability of High Density Wiring (HDW) substrates through new dielectric and base substrate materials Asme International Mechanical Engineering Congress and Exposition, Proceedings. 283-290. DOI: 10.1115/IMECE2002-39671  0.325
2002 Modi MB, Sitaraman SK. Modified decohesion test (MDT) for interfacial fracture toughness measurement in microelectronic/MEMS applications Asme International Mechanical Engineering Congress and Exposition, Proceedings. 277-282. DOI: 10.1115/IMECE2002-39670  0.671
2002 Dunne RC, Sitaraman SK. An integrated process modeling methodology and module for sequential multilayered substrate fabrication using a coupled cure-thermal-stress analysis approach Ieee Transactions On Electronics Packaging Manufacturing. 25: 326-334. DOI: 10.1109/TEPM.2002.807733  0.716
2002 Dunne RC, Sitaraman SK, Luo S, Wong CP, Estes WE, Periyasamy M. Cure kinetics modeling and process optimization of the ViaLux 81 epoxy photodielectric dry film (PDDF) material for microvia applications Journal of Applied Polymer Science. 84: 691-700. DOI: 10.1002/App.2345  0.678
2001 Dunne RC, Sitaraman SK, Luo S, Wong CP, Estes WE, Periyasamy M, Coburn J. Thermal and mechanical characterization of ViaLux™ 81: A novel epoxy photo-dielectric dry film (PDDF) for microvia applications Ieee Transactions On Components and Packaging Technologies. 24: 436-444. DOI: 10.1109/6144.946491  0.691
2001 Harries RJ, Sitaraman SK. Numerical modeling of interfacial delamination propagation in a novel peripheral array package Ieee Transactions On Components and Packaging Technologies. 24: 256-263. DOI: 10.1109/6144.926391  0.302
2001 Ma L, Zhu Q, Sitaraman S. Alternative compliant interconnects - Thermo-mechanical reliability, design and testing Asme International Mechanical Engineering Congress and Exposition, Proceedings. 2: 2095-2104.  0.318
2001 Zhu Q, Ma L, Sitaraman SK. Mechanical and Preliminary Electrical Design of a Novel Compliant One-Turn Helix (OTH) Interconnect Advances in Electronic Packaging. 3: 1891-1896.  0.319
2001 Xie W, Hu H, Sitaraman SK. Determining interfacial delamination propagation of ViaLux™ 81/ copper interface in multelayered System-On-Package (SOP) integrated substrates Advances in Electronic Packaging. 1: 351-356.  0.324
2000 Fork DK, Chua C, Kim P, Romano L, Lau R, Wong L, Alimonda AS, Geluz V, Teepe M, Haemer J, Modi M, Zhu QA, Ma D, Sitaraman S, Smith DL, et al. Nano-spring arrays for high-density interconnect Proceedings of Spie. 4176: 226-235. DOI: 10.1117/12.395634  0.705
1999 Variyam MN, Xie W, Sitaraman SK. Role of Out-of-Plane Coefficient of Thermal Expansion in Electronic Packaging Modeling Journal of Electronic Packaging. 122: 121-127. DOI: 10.1115/1.483143  0.479
1999 Michaelides S, Sitaraman SK. Die cracking and reliable die design for flip-chip assemblies Ieee Transactions On Advanced Packaging. 22: 602-613. DOI: 10.1109/6040.803452  0.305
1999 Harries RJ, Sitaraman SK. Numerical study of copper-encapsulant interfacial delamination propagation in a peripheral array package American Society of Mechanical Engineers, Eep. 26.  0.306
1997 Dunne RC, Sitaraman SK. Warpage and Interfacial Stress Distribution in a Single-Level Integrated Module (SLIM) Journal of Electronic Packaging, Transactions of the Asme. 119: 197-203. DOI: 10.1115/1.2792234  0.695
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