Anand Raghunathan - Publications

Affiliations: 
Electrical and Computer Engineering Purdue University, West Lafayette, IN, United States 
Area:
Computer Engineering, Computer Science

132 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Jain S, Sengupta A, Roy K, Raghunathan A. RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.3000185  0.44
2019 Chen M, Ranjan A, Raghunathan A, Roy K. Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack Ieee Transactions On Magnetics. 55: 1-9. DOI: 10.1109/Tmag.2019.2909188  0.44
2019 Venkataramani S, Kozhikkottu V, Sabne A, Roy K, Raghunathan A. Logic Synthesis of Approximate Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2019.2940680  0.44
2018 Sarwar SS, Venkataramani S, Ankit A, Raghunathan A, Roy K. Energy-Efficient Neural Computing with Approximate Multipliers Acm Journal On Emerging Technologies in Computing Systems. 14: 16. DOI: 10.1145/3097264  0.44
2018 Jain S, Ranjan A, Roy K, Raghunathan A. Computing in Memory With Spin-Transfer Torque Magnetic RAM Ieee Transactions On Very Large Scale Integration Systems. 26: 470-483. DOI: 10.1109/Tvlsi.2017.2776954  0.44
2018 Sarwar SS, Srinivasan G, Han B, Wijesinghe P, Jaiswal A, Panda P, Raghunathan A, Roy K. Energy Efficient Neural Computing: A Study of Cross-Layer Approximations Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 796-809. DOI: 10.1109/Jetcas.2018.2835809  0.44
2017 Goud AA, Venkatesan R, Raghunathan A, Roy K. Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes Acm Journal On Emerging Technologies in Computing Systems. 13: 23. DOI: 10.1145/2967615  0.44
2016 Sengupta A, Panda P, Raghunathan A, Roy K. Neuromorphic Computing Enabled by Spin-Transfer Torque Devices Proceedings of the Ieee International Conference On Vlsi Design. 2016: 32-37. DOI: 10.1109/VLSID.2016.117  0.6
2016 Raha A, Venkataramani S, Raghunathan V, Raghunathan A. Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2586379  0.6
2016 Liu J, Venkataramani S, Venkatakrishnan SV, Pan Y, Bouman CA, Raghunathan A. EMBIRA: An Accelerator for Model-Based Iterative Reconstruction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2016.2551204  0.6
2016 Mohsen Nia A, Sur-Kolay S, Raghunathan A, Jha NK. Physiological Information Leakage: A New Frontier in Health Information Security Ieee Transactions On Emerging Topics in Computing. 4: 321-334. DOI: 10.1109/Tetc.2015.2478003  0.6
2016 Akkala AG, Venkatesan R, Raghunathan A, Roy K. Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2512227  0.6
2016 Fong X, Kim Y, Yogendra K, Fan D, Sengupta A, Raghunathan A, Roy K. Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1-22. DOI: 10.1109/Tcad.2015.2481793  0.6
2016 Venkatesan R, Kozhikkottu VJ, Sharad M, Augustine C, Raychowdhury A, Roy K, Raghunathan A. Cache Design with Domain Wall Memory Ieee Transactions On Computers. 65: 1010-1024. DOI: 10.1109/Tc.2015.2506581  0.6
2016 Roy K, Jung B, Peroulis D, Raghunathan A. Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components Ieee Design and Test. 33: 56-65. DOI: 10.1109/Mdt.2011.49  0.6
2015 Mozaffari-Kermani M, Sur-Kolay S, Raghunathan A, Jha NK. Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. Ieee Journal of Biomedical and Health Informatics. 19: 1893-905. PMID 25095272 DOI: 10.1109/Jbhi.2014.2344095  0.6
2015 Mirtar A, Dey S, Raghunathan A. An application adaptation approach to mitigate the impact of dynamic thermal management on video encoding Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2753758  0.6
2015 Kim Y, Lee WS, Raghunathan V, Jha NK, Raghunathan A. Vibration-based secure side channel for medical devices Proceedings - Design Automation Conference. 2015. DOI: 10.1145/2744769.2744928  0.6
2015 Venkatesan R, Sharad M, Roy K, Raghunathan A. Energy-efficient all-spin cache hierarchy using shift-based writes and multilevel storage Acm Journal On Emerging Technologies in Computing Systems. 12. DOI: 10.1145/2723165  0.6
2015 Fong X, Venkatesan R, Lee D, Raghunathan A, Roy K. Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2015.2439733  0.6
2015 Mirtar A, Dey S, Raghunathan A. Joint work and voltage/frequency scaling for quality-optimized dynamic thermal management Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1017-1030. DOI: 10.1109/Tvlsi.2014.2333741  0.6
2015 Fan D, Shim Y, Raghunathan A, Roy K. STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks Ieee Transactions On Nanotechnology. 14: 1013-1023. DOI: 10.1109/Tnano.2015.2437902  0.6
2015 Pajouhi Z, Venkataramani S, Yogendra K, Raghunathan A, Roy K. Exploring Spin-Transfer-Torque Devices for Logic Applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1441-1454. DOI: 10.1109/Tcad.2015.2413852  0.6
2015 Roy K, Raghunathan A. Approximate computing: An energy-efficient computing technique for error resilient applications Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 7: 473-475. DOI: 10.1109/ISVLSI.2015.130  0.6
2015 Kim Y, Raghunathan V, Raghunathan A. Design and management of hybrid electrical energy storage systems for regulation services 2014 International Green Computing Conference, Igcc 2014. DOI: 10.1109/IGCC.2014.7039177  0.6
2015 Kim Y, Lee W, Raghunathan A, Raghunathan V, Jha NK. Reliability and security of implantable and wearable medical devices Implantable Biomedical Microsystems: Design Principles and Applications. 167-199. DOI: 10.1016/B978-0-323-26208-8.00008-X  0.6
2015 Raha A, Venkataramani S, Raghunathan V, Raghunathan A. Quality configurable reduce-and-rank for energy efficient approximate computing Proceedings -Design, Automation and Test in Europe, Date. 2015: 665-670.  0.6
2014 Chippa VK, Mohapatra D, Roy K, Chakradhar ST, Raghunathan A. Scalable effort hardware design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 2004-2016. DOI: 10.1109/Tvlsi.2013.2276759  0.6
2014 Venkatesan R, Chippa VK, Augustine C, Roy K, Raghunathan A. Domain-Specific Many-core Computing using Spin-based Memory Ieee Transactions On Nanotechnology. 13: 881-894. DOI: 10.1109/Tnano.2014.2306958  0.6
2014 Fong X, Venkatesan R, Raghunathan A, Roy K. Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective Ieee Transactions On Magnetics. 50. DOI: 10.1109/Tmag.2014.2326858  0.6
2014 Zhang M, Raghunathan A, Jha NK. Trustworthiness of medical devices and body area networks Proceedings of the Ieee. 102: 1174-1188. DOI: 10.1109/JPROC.2014.2322103  0.6
2014 Zhang M, Raghunathan A, Jha NK. A defense framework against malware and vulnerability exploits International Journal of Information Security. 13: 439-452. DOI: 10.1007/S10207-014-0233-1  0.6
2013 Chippa VK, Roy K, Chakradhar ST, Raghunathan A. Managing the quality vs. efficiency trade-off using dynamic effort scaling Transactions On Embedded Computing Systems. 12. DOI: 10.1145/2465787.2465792  0.6
2013 Zhang M, Raghunathan A, Jha NK. Towards trustworthy medical devices and body area networks Proceedings - Design Automation Conference. DOI: 10.1145/2463209.2488751  0.6
2013 Gupta V, Mohapatra D, Raghunathan A, Roy K. Low-Power Digital Signal Processing Using Approximate Adders Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 124-137. DOI: 10.1109/Tcad.2012.2217962  0.44
2013 Li C, Raghunathan A, Jha NK. Improving the trustworthiness of medical device software with formal verification methods Ieee Embedded Systems Letters. 5: 50-53. DOI: 10.1109/Les.2013.2276434  0.6
2013 Sharad M, Venkatesan R, Raghunathan A, Roy K. Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches Proceedings of the International Symposium On Low Power Electronics and Design. 64-69. DOI: 10.1109/ISLPED.2013.6629268  0.6
2013 Rabbah R, Raghunathan A. Message from the program co-chairs 2013 International Conference On Compilers, Architecture and Synthesis For Embedded Systems, Cases 2013. DOI: 10.1109/CASES.2013.6662501  0.6
2013 Chuah JW, Raghunathan A, Jha NK. ROBESim: A retrofit-oriented building energy simulator based on EnergyPlus Energy and Buildings. 66: 88-103. DOI: 10.1016/J.Enbuild.2013.07.020  0.6
2013 Venkataramani S, Roy K, Raghunathan A. Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits Proceedings -Design, Automation and Test in Europe, Date. 1367-1372.  0.6
2012 Kozhikkottu V, Dey S, Raghunathan A. Recovery-based design for variation-tolerant SoCs Proceedings - Design Automation Conference. 826-833. DOI: 10.1145/2228360.2228510  0.6
2012 Li C, Jha NK, Raghunathan A. Secure reconfiguration of software-defined radio Transactions On Embedded Computing Systems. 11. DOI: 10.1145/2146417.2146427  0.6
2012 Griffin WP, Raghunathan A, Roy K. CLIP: Circuit level IC protection through direct injection of process variations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 791-803. DOI: 10.1109/Tvlsi.2011.2135868  0.6
2012 Li C, Raghunathan A, Jha NK. A trusted virtual machine in an untrusted management environment Ieee Transactions On Services Computing. 5: 472-483. DOI: 10.1109/Tsc.2011.30  0.6
2012 Pienaar JA, Chakradhar S, Raghunathan A. Automatic generation of software pipelines for heterogeneous parallel systems International Conference For High Performance Computing, Networking, Storage and Analysis, Sc. DOI: 10.1109/SC.2012.22  0.6
2012 Agarwal Y, Raghunathan A. Guest editors' introduction: Green buildings Ieee Design and Test of Computers. 29: 5-7. DOI: 10.1109/Mdt.2012.2202574  0.6
2012 Mirtar A, Dey S, Raghunathan A. Adaptation of video encoding to address dynamic thermal management effects 2012 International Green Computing Conference, Igcc 2012. DOI: 10.1109/IGCC.2012.6322294  0.6
2011 Raghunathan A, Murugesan K. Performance-enhanced caching scheme for web clusters for dynamic content International Journal of Business Data Communications and Networking. 7: 16-36. DOI: 10.4018/jbdcn.2011070102  0.6
2011 Pienaar JA, Raghunathan A, Chakradhar S. MDR: Performance model driven runtime for heterogeneous parallel platforms Proceedings of the International Conference On Supercomputing. 225-234. DOI: 10.1145/1995896.1995933  0.6
2011 Li C, Raghunathan A, Jha NK. Hijacking an insulin pump: Security attacks and defenses for a diabetes therapy system 2011 Ieee 13th International Conference On E-Health Networking, Applications and Services, Healthcom 2011. 150-156. DOI: 10.1109/HEALTH.2011.6026732  0.6
2011 Chandrachoodan N, Karthik S, Raghunathan A. Message from the program chairs Proceedings of the Ieee International Conference On Vlsi Design. xii-xiii.  0.6
2010 Chakradhar ST, Raghunathan A. Best-effort computing: Re-thinking parallel software and hardware Proceedings - Design Automation Conference. 865-870. DOI: 10.1145/1837274.1837492  0.6
2010 Roy K, Jung B, Raghunathan A. Integrated systems in the more-than-moore era: Designing low-cost energy-efficient systems using heterogeneous components Proceedings of the Ieee International Conference On Vlsi Design. 464-469. DOI: 10.1109/VLSI.Design.2010.84  0.6
2010 Chandra S, Lahiri K, Raghunathan A, Dey S. Variation-aware system-level power analysis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 1173-1184. DOI: 10.1109/Tvlsi.2009.2021478  0.6
2010 Meng J, Raghunathan A, Chakradhar S, Byna S. Exploiting the forgiving nature of applications for scalable parallel execution Proceedings of the 2010 Ieee International Symposium On Parallel and Distributed Processing, Ipdps 2010. DOI: 10.1109/IPDPS.2010.5470469  0.6
2010 Li C, Raghunathan A, Jha NK. A secure user interface for web applications running under an untrusted operating system Proceedings - 10th Ieee International Conference On Computer and Information Technology, Cit-2010, 7th Ieee International Conference On Embedded Software and Systems, Icess-2010, Scalcom-2010. 865-870. DOI: 10.1109/CIT.2010.162  0.6
2009 Sundaram N, Raghunathan A, Chakradhar ST. A framework for efficient and scalable execution of domain-specific templates on GPUs Ipdps 2009 - Proceedings of the 2009 Ieee International Parallel and Distributed Processing Symposium. DOI: 10.1109/IPDPS.2009.5161039  0.6
2009 Meng J, Chakradhar S, Raghunathan A. Best-effort parallel execution framework for recognition and mining applications Ipdps 2009 - Proceedings of the 2009 Ieee International Parallel and Distributed Processing Symposium. DOI: 10.1109/IPDPS.2009.5160991  0.6
2008 Aaraj N, Raghunathan A, Jha NK. Analysis and design of a hardware/software trusted platform module for embedded systems Transactions On Embedded Computing Systems. 8. DOI: 10.1145/1457246.1457254  0.6
2008 Thoguluva J, Raghunathan A, Chakradhar ST. Efficient software architecture for IPSec acceleration using a programmable security processor Proceedings -Design, Automation and Test in Europe, Date. 1148-1153. DOI: 10.1109/DATE.2008.4484833  0.6
2008 Aaraj N, Raghunathan A, Jha NK. Dynamic binary instrumentation-based framework for malware defense Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5137: 64-87. DOI: 10.1007/978-3-540-70542-0_4  0.6
2007 Bansal N, Lahiri K, Raghunathan A. Automatic power modeling of infrastructure IP for systemonchip power analysis Proceedings of the Ieee International Conference On Vlsi Design. 513-520. DOI: 10.1109/VLSID.2007.46  0.6
2007 Arora D, Raghunathan A, Ravi S, Sankaradass M, Jha NK, Chakradhar ST. Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC Ieee Transactions On Very Large Scale Integration Systems. 15: 699-710. DOI: 10.1109/Tvlsi.2007.898740  0.44
2007 Muttreja A, Raghunathan A, Ravi S, Jha NK. Hybrid simulation for energy estimation of embedded software Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1843-1854. DOI: 10.1109/Tcad.2007.895760  0.6
2007 Schaumont P, Raghunathan A. Guest editors' introduction: Security and trust in embedded-systems design Ieee Design and Test of Computers. 24: 518-520. DOI: 10.1109/Mdt.2007.188  0.6
2007 Ghodrat MA, Lahiri K, Raghunathan A. Accelerating system-on-chip power analysis using hybrid power estimation Proceedings - Design Automation Conference. 883-886. DOI: 10.1109/DAC.2007.375288  0.6
2007 Sun F, Ravi S, Raghunathan A, Jha NK. A framework for extensible processor based MPSoC design Designing Embedded Processors: a Low Power Perspective. 65-95. DOI: 10.1007/978-1-4020-5869-1_4  0.6
2006 Sun F, Ravi S, Raghunathan A, Jha NK. Hybrid custom instruction and co-processor synthesis methodology for extensible processors Proceedings of the Ieee International Conference On Vlsi Design. 2006: 473-476. DOI: 10.1109/VLSID.2006.100  0.6
2006 Psarakis M, Gizopoulos D, Hatzimihail M, Paschalis A, Raghunathan A, Ravi S. Systematic software-based self-test for pipelined processors Proceedings - Design Automation Conference. 393-398. DOI: 10.1109/Tvlsi.2008.2000866  0.6
2006 Lahiri K, Raghunathan A, Lakshminarayana G. The LOTTERYBUS on-chip communication architecture Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 596-608. DOI: 10.1109/Tvlsi.2006.878210  0.6
2006 Potlapally NR, Ravi S, Raghunathan A, Jha NK. A study of the energy consumption characteristics of cryptographic algorithms and security protocols Ieee Transactions On Mobile Computing. 5: 128-143. DOI: 10.1109/Tmc.2006.16  0.6
2006 Lingappan L, Ravi S, Raghunathan A, Jha NK, Chakradhar ST. Test-volume reduction in systems-on-a-chip using heterogeneous and multilevel compression techniques Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2193-2205. DOI: 10.1109/Tcad.2005.862735  0.6
2006 Zhong L, Ravi S, Raghunathan A, Jha NK. RTL-aware cycle-accurate functional power estimation Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2103-2116. DOI: 10.1109/Tcad.2005.859504  0.6
2006 Muttreja A, Raghunathan A, Ravi S, Jha NK. Active learning driven data acquisition for sensor networks Proceedings - International Symposium On Computers and Communications. 929-934. DOI: 10.1109/ISCC.2006.23  0.6
2006 Sekar K, Lahiri K, Raghunathan A, Dey S. Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms Proceedings -Design, Automation and Test in Europe, Date. 1.  0.6
2006 Stanley-Marbell P, Lahiri K, Raghunathan A. Adaptive data placement in an embedded multiprocessor thread library Proceedings -Design, Automation and Test in Europe, Date. 1.  0.6
2005 Wang W, Raghunathan A, Lakshminarayana G, Jha NK. Input space-adaptive optimization for embedded-software synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1677-1692. DOI: 10.1109/Tcad.2005.852282  0.6
2005 Park C, Lahiri K, Raghunathan A. Battery discharge characteristics of wireless sensor nodes: An experimental analysis 2005 Second Annual Ieee Communications Society Conference On Sensor and Adhoc Communications and Networks, Secon 2005. 2005: 430-440. DOI: 10.1109/SAHCN.2005.1557096  0.6
2005 Sun F, Ravi S, Raghunathan A, Jha NK. Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors Proceedings of the Ieee International Conference On Vlsi Design. 551-556. DOI: 10.1109/ICVD.2005.155  0.6
2005 Coburn J, Ravi S, Raghunathan A. Hardware accelerated power estimation Proceedings -Design, Automation and Test in Europe, Date '05. 528-529. DOI: 10.1109/DATE.2005.168  0.6
2005 Lahiri K, Dey S, Raghunathan A. Design of Communication Architectures for High-Performance and Energy-Efficient Systems-on-Chips Multiprocessor Systems-On-Chips. 187-222. DOI: 10.1016/B978-012385251-9/50021-9  0.6
2005 Muttreja A, Raghunathan A, Ravi S, Jha NK. Hybrid simulation for embedded software energy estimation Proceedings - Design Automation Conference. 23-26.  0.6
2005 Roy K, Tiwari V, Raghunathan A, Stan M. Proceedings of the International Symposium on Low Power Electronics and Design: Foreword Proceedings of the International Symposium On Low Power Electronics and Design 0.6
2005 Gupta P, Ravi S, Raghunathan A, Jha NK. Efficient fingerprint-based user authentication for embedded systems Proceedings - Design Automation Conference. 244-247.  0.6
2005 Coburn J, Ravi S, Raghunathan A. Power emulation: A new paradigm for power estimation Proceedings - Design Automation Conference. 700-705.  0.6
2004 Muttreja A, Raghunathan A, Ravi S, Jha NK. Automated energy/performance macromodeling of embedded software Proceedings - Design Automation Conference. 99-102. DOI: 10.1109/Tcad.2006.883914  0.6
2004 Lahiri K, Raghunathan A, Dey S. Efficient power profiling for battery-driven embedded system design Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 919-932. DOI: 10.1109/Tcad.2004.828137  0.6
2004 Lahiri K, Raghunathan A, Dey S. Design space exploration for optimizing on-chip communication architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 952-961. DOI: 10.1109/Tcad.2004.828127  0.6
2004 Lahiri K, Raghunathan A, Lakshminarayana G, Dey S. Design of high-performance system-on-chips using communication architecture tuners Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 620-636. DOI: 10.1109/Tcad.2004.826585  0.6
2004 Lakshminarayana G, Raghunathan A, Khouri KS, Jha NK, Dey S. Common-Case Computation: A High-Level Energy and Performance Optimization Technique Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 33-49. DOI: 10.1109/Tcad.2003.819893  0.6
2004 Lahiri K, Raghunathan A. Power analysis of system-level on-chip communication architectures Second Ieee/Acm/Ifip International Conference On Hardware/Software Codesign and Systems Synthesis, Codes+Isss 2004. 236-241.  0.6
2004 Zhong L, Ravi S, Raghunathan A, Jha NK. Power estimation for cycle-accurate functional descriptions of hardware Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 668-675.  0.6
2004 Wang W, Raghunathan A, Jha NK. Profiling driven computation reuse: An embedded software synthesis technique for energy and performance optimization Proceedings of the Ieee International Conference On Vlsi Design. 17: 267-272.  0.6
2003 Raghunathan A, Dey S, Jha NK. High-Level Macro-Modeling and Estimation Techniques for Switching Activity and Power Consumption Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 538-557. DOI: 10.1109/Tvlsi.2003.812295  0.6
2003 Ravi S, Raghunathan A, Chakradhar S. Efficient RTL power estimation for large designs Proceedings of the Ieee International Conference On Vlsi Design. 2003: 431-439. DOI: 10.1109/ICVD.2003.1183173  0.6
2003 Tan TK, Raghunathan A, Jha NK. Software architectural transformations: A new approach to low energy embedded software Proceedings -Design, Automation and Test in Europe, Date. 1046-1051. DOI: 10.1109/DATE.2003.1253742  0.6
2003 Raghunathan A, Ravi S, Hattangady S, Quisquater JJ. Securing mobile appliances: New challenges for the system designer Proceedings -Design, Automation and Test in Europe, Date. 176-181. DOI: 10.1109/DATE.2003.1253605  0.6
2003 Ganesh G, Ravi S, Raghunathan A. A provisioning algorithm for revenue maximization in optical networks Proceedings of the Iasted International Conference On Wireless and Optical Communications. 3: 80-85.  0.6
2003 Sun F, Ravi S, Raghunathan A, Jha NK. A Scalable Application-Specific Processor Synthesis Methodology Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 283-290.  0.6
2003 Potlapally NR, Ravi S, Raghunathan A, Jha NK. Analyzing the Energy Consumption of Security Protocols Proceedings of the International Symposium On Low Power Electronics and Design. 30-35.  0.6
2002 Sun F, Ravi S, Raghunathan A, Jha NK. Synthesis of custom processors based on extensible platforms Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 641-648. DOI: 10.1145/774572.774667  0.6
2002 Tan TK, Raghunathan A, Lakshminarayana G, Jha NK. High-level energy macromodeling of embedded software Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1037-1050. DOI: 10.1109/Tcad.2002.801094  0.6
2002 Lahiri K, Raghunathan A, Dey S. Communication-based power management Ieee Design and Test of Computers. 19: 118-130. DOI: 10.1109/Mdt.2002.1018140  0.6
2002 Raghunathan V, Raghunathan A, Srivastava MB, Ercegovac MD. High-level synthesis with SIMD units Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 407-413. DOI: 10.1109/ASPDAC.2002.994955  0.6
2002 Lahiri K, Raghunathan A, Dey S, Panigrahi D. Battery-driven system design: A new frontier in low power design Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 261-267. DOI: 10.1109/ASPDAC.2002.994932  0.6
2002 Lahiri K, Raghunathan A, Dey S. Fast system-level power profiling for battery-efficient system design Hardware/Software Codesign - Proceedings of the International Workshop. 157-162.  0.6
2002 Lahiri K, Raghunathan A, Dey S. Battery-efficient architecture for an 802.11 MAC processor Ieee International Conference On Communications. 2: 669-674.  0.6
2002 Chang J, Ravi S, Raghunathan A. FLEXBAR: A crossbar switching fabric with improved performance and utilization Proceedings of the Custom Integrated Circuits Conference. 405-408.  0.6
2002 Lahiri K, Raghunathan A, Dey S. Communication architecture based power management for battery efficient system design Proceedings - Design Automation Conference. 691-696.  0.6
2002 Tan TK, Raghunathan A, Jha NK. Embedded operating system energy analysis and macro-modeling Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 515-522.  0.6
2002 Tan TK, Raghunathan A, Jha NK. EMSIM: An energy simulation framework for an embedded operating system Proceedings - Ieee International Symposium On Circuits and Systems. 2.  0.6
2002 Ravi S, Raghunathan A, Potlapally N, Sankaradass M. System design methodologies for a wireless security processing platform Proceedings - Design Automation Conference. 777-782.  0.6
2002 Potlapally NR, Ravi S, Raghunathan A, Lakshminarayana G. Optimizing public-key encryption for wireless clients Ieee International Conference On Communications. 2: 1050-1056.  0.6
2002 Ravi S, Raghunathan A, Potlapally N. Securing wireless data: System architecture challenges Proceedings of the International Symposium On System Synthesis. 195-200.  0.6
2001 Lahiri K, Raghunathan A, Dey S. System-level performance analysis for designing on-chip communication architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 768-783. DOI: 10.1109/43.924830  0.6
2001 Raghunathan A, Dey S. Tutorial: Low-power mobile wireless communication system design: Protocols, architectures, and design methodologies Proceedings of the Ieee International Conference On Vlsi Design. 9-10.  0.6
2001 Raghunathan V, Ravi S, Raghunathan A, Lakshminarayana G. Transient power management through high level synthesis Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers. 545-552.  0.6
2001 Lahiri K, Raghunathan A, Lakshminarayana G. LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs Proceedings - Design Automation Conference. 15-20.  0.6
2001 Lahiri K, Raghunathan A, Dey S. Evaluation of the traffic-performance characteristics of system-on-chip communication architectures Proceedings of the Ieee International Conference On Vlsi Design. 29-35.  0.6
2001 Panigrahi D, Raghunathan A, Lakshminarayana G, Dey S. Energy modeling for wireless internet access Proceedings - 2001 International Conference On Third Generation Wireless and Beyond. 332-337.  0.6
2001 Wang W, Raghunathan A, Lakshminarayana G, Jha NK. Input space adaptive design: A high-level methodology for energy and performance optimization Proceedings - Design Automation Conference. 738-743.  0.6
2001 Tan TK, Raghunathan A, Lakshminarayana G, Jha NK. High-level software energy macro-modeling Proceedings - Design Automation Conference. 605-610.  0.6
2000 Lakshminarayana G, Raghunathan A, Jha NK. Incorporating speculative execution into scheduling of control-flow-intensive designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 308-324. DOI: 10.1109/43.833200  0.6
1999 Lakshminarayana G, Raghunathan A, Jha NK, Dey S. Power management in high-level synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 7-15. DOI: 10.1109/92.748195  0.6
1999 Raghunathan A, Dey S, Jha NK. Register transfer level power optimization with emphasis on glitch analysis and reduction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 1114-1131. DOI: 10.1109/43.775632  0.6
1999 Ghosh I, Raghunathan A, Jha NK. Hierarchical test generation and design for testability methods for aspp's and ASIP's Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 18: 357-370.  0.6
1998 Ghosh I, Raghunathan A, Jha NK. A design-for-testability technique for register-transfer level circuits using control/data flow extraction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 706-723. DOI: 10.1109/43.712102  0.6
1998 Dey S, Raghunathan A, Wagner KD. Design for Testability Techniques at the Behavioral and Register-Transfer Levels Journal of Electronic Testing: Theory and Applications (Jetta). 13: 79-91.  0.6
1997 Raghunathan A, Jha NK. SCALP: An iterative-improvement-based low-power data path synthesis system Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1260-1277. DOI: 10.1109/43.663817  0.6
1997 Chakradhar ST, Raghunathan A. Bottleneck removal algorithm for dynamic compaction in sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1157-1172. DOI: 10.1109/43.662677  0.6
1997 Ghosh I, Raghunathan A, Jha NK. Design for hierarchical testability of RTL circuits obtained by behavioral synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 1001-1014. DOI: 10.1109/43.658568  0.6
1995 Raghunathan A, Malik S, Ashar P. Test Generation for Cyclic Combinational Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 14: 1408-1414. DOI: 10.1109/43.469666  0.6
Show low-probability matches.