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Borivoje Nikolic - Publications

Affiliations: 
Electrical Engineering and Computer Science University of California, Berkeley, Berkeley, CA, United States 
Area:
Integrated Circuits (INC); Communications & Networking (COMNET); Design, Modeling and Analysis (DMA); Computer Architecture & Engineering (ARC)
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66 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Zhao B, Kuo N, Niknejad AM, Nikolic B. A Line-Array Technique for Wireless Power Transfer Toward a 100 $\mu$ m $\times100$ $\mu$ m Coil Antenna Ieee Transactions On Microwave Theory and Techniques. 68: 353-364. DOI: 10.1109/Tmtt.2019.2940016  0.331
2020 Amid A, Biancolin D, Gonzalez A, Grubb D, Karandikar S, Liew H, Magyar A, Mao H, Ou A, Pemberton N, Rigge P, Schmidt C, Wright J, Zhao J, Shao YS, ... ... Nikolic B, et al. Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs Ieee Micro. 40: 10-21. DOI: 10.1109/Mm.2020.2996616  0.332
2019 Celio C, Chiu P, Asanovic K, Nikolic B, Patterson D. BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS Ieee Micro. 39: 52-60. DOI: 10.1109/Mm.2019.2897782  0.395
2019 Bailey S, Rigge P, Han J, Lin R, Chang EY, Mao H, Wang Z, Markley C, Izraelevitz AM, Wang A, Narevsky N, Bae W, Shauck S, Montano S, Norsworthy J, ... ... Nikolic B, et al. A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance Ieee Journal of Solid-State Circuits. 54: 2786-2801. DOI: 10.1109/Jssc.2019.2924090  0.399
2019 Wang A, Bae W, Han J, Bailey S, Ocal O, Rigge P, Wang Z, Ramchandran K, Alon E, Nikolic B. A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET Ieee Journal of Solid-State Circuits. 54: 1993-2008. DOI: 10.1109/Jssc.2019.2913099  0.4
2019 Swamy VN, Rigge P, Ranade G, Nikolic B, Sahai A. Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications Ieee Journal On Selected Areas in Communications. 37: 705-720. DOI: 10.1109/Jsac.2019.2900784  0.324
2018 Kuo N, Yang B, Wang A, Kong L, Wu C, Srini VP, Alon E, Nikolic B, Niknejad AM. A 0.4-to-4-GHz All-Digital RF Transmitter Package With a Band-Selecting Interposer Combining Three Wideband CMOS Transmitters Ieee Transactions On Microwave Theory and Techniques. 66: 4967-4984. DOI: 10.1109/Tmtt.2018.2860007  0.358
2018 Bae W, Yoon KJ, Song T, Nikolic B. A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique Ieee Transactions On Circuits and Systems Ii-Express Briefs. 65: 1839-1843. DOI: 10.1109/Tcsii.2018.2868460  0.316
2018 Yang B, Chang EY, Niknejad AM, Nikolic B, Alon E. A 65-nm CMOS $I/Q$ RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering Ieee Journal of Solid-State Circuits. 53: 1127-1138. DOI: 10.1109/Jssc.2017.2782084  0.359
2017 Swamy VN, Suri S, Rigge P, Weiner M, Ranade G, Sahai A, Nikolic B. Real-Time Cooperative Communication for Automation Over Wireless Ieee Transactions On Wireless Communications. 16: 7168-7183. DOI: 10.1109/Twc.2017.2741485  0.32
2017 Bae W, Nikolic B, Jeong D. Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis Ieee Transactions On Very Large Scale Integration Systems. 25: 3543-3547. DOI: 10.1109/Tvlsi.2017.2747157  0.333
2017 Kuo N, Yang B, Wang A, Kong L, Wu C, Srini VP, Alon E, Nikolic B, Niknejad AM. A Wideband All-Digital CMOS RF Transmitter on HDI Interposers With High Power and Efficiency Ieee Transactions On Microwave Theory and Techniques. 65: 4724-4743. DOI: 10.1109/Tmtt.2017.2731309  0.379
2017 Zimmer B, Chiu P, Nikolic B, Asanovic K. Reprogrammable Redundancy for SRAM-Based Cache $V_{\min }$ Reduction in a 28-nm RISC-V Processor Ieee Journal of Solid-State Circuits. 52: 2589-2600. DOI: 10.1109/Jssc.2017.2715798  0.378
2017 Xiao X, Pratt A, Yang B, Wang A, Niknejad AM, Alon E, Nikolic B. A 65-nm CMOS Wideband TDD Front-End With Integrated T/R Switching via PA Re-Use Ieee Journal of Solid-State Circuits. 52: 1768-1782. DOI: 10.1109/Jssc.2017.2702669  0.333
2017 Calderin L, Ramakrishnan S, Puglielli A, Alon E, Nikolic B, Niknejad AM. Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems Ieee Journal of Solid-State Circuits. 52: 2038-2054. DOI: 10.1109/Jssc.2017.2700360  0.366
2017 Keller B, Cochet M, Zimmer B, Kwak J, Puggelli A, Lee Y, Blagojevic M, Bailey S, Chiu P, Dabbelt P, Schmidt C, Alon E, Asanovic K, Nikolic B. A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI Ieee Journal of Solid-State Circuits. 52: 1863-1875. DOI: 10.1109/Jssc.2017.2690859  0.362
2016 Wu C, Wang Y, Nikolic B, Hull C. An Interference-Resilient Wideband Mixer-First Receiver With LO Leakage Suppression and I/Q Correlated Orthogonal Calibration Ieee Transactions On Microwave Theory and Techniques. DOI: 10.1109/Tmtt.2016.2532867  0.418
2016 Kwak J, Nikolic B. A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI Ieee Journal of Solid-State Circuits. 51: 2368-2379. DOI: 10.1109/Jssc.2016.2582860  0.417
2016 Zimmer B, Lee Y, Puggelli A, Kwak J, Jevtic R, Keller B, Bailey S, Blagojevic M, Chiu PF, Le HP, Chen PH, Sutardja N, Avizienis R, Waterman A, Richards B, ... ... Nikolic B, et al. A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI Ieee Journal of Solid-State Circuits. DOI: 10.1109/Jssc.2016.2519386  0.36
2015 Jevtić R, Le HP, Blagojević M, Bailey S, Asanović K, Alon E, Nikolić B. Per-Core DVFS with Switched-Capacitor Converters for Energy Efficiency in Manycore Processors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 723-730. DOI: 10.1109/Tvlsi.2014.2316919  0.366
2015 Chiu PF, Nikolić B. A differential 2R crosspoint RRAM array with zero standby current Ieee Transactions On Circuits and Systems Ii: Express Briefs. 62: 461-465. DOI: 10.1109/Tcsii.2014.2385431  0.324
2014 Wu C, Alon E, Nikolic B. A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode ΔΣ Receiver Ieee Journal of Solid-State Circuits. 49: 1639-1652. DOI: 10.1109/Jssc.2014.2319249  0.4
2013 Stepanovic D, Nikolic B. A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS Ieee Journal of Solid-State Circuits. 48: 971-982. DOI: 10.1109/Jssc.2013.2239005  0.423
2013 Nagpal V, Wang IH, Jorgovanovic M, Tse D, Nikolić B. Coding and system design for quantize-map-and-forward relaying Ieee Journal On Selected Areas in Communications. 31: 1423-1435. DOI: 10.1109/Jsac.2013.130807  0.725
2013 Jorgovanovic M, Weiner M, Tse D, Nikolic B, Wang IH, Nagpal V. Relay scheduling and interference cancellation for quantize-map-and-forward cooperative relaying Ieee International Symposium On Information Theory - Proceedings. 1959-1963. DOI: 10.1109/ISIT.2013.6620568  0.71
2012 Hoyos S, Tsang CW, Vanderhaegen J, Chiu Y, Aibara Y, Khorramabadi H, Nikolic B. A 15 MHz to 600 MHz, 20 mW, 0.38 mm 2 split-control, fast coarse locking digital DLL in 0.13 μ m CMOS Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 564-568. DOI: 10.1109/Tvlsi.2011.2106170  0.707
2012 Zimmer B, Toh SO, Vo H, Lee Y, Thomas O, Asanovic K, Nikolic B. SRAM assist techniques for operation in a wide voltage range in 28-nm CMOS Ieee Transactions On Circuits and Systems Ii: Express Briefs. 59: 853-857. DOI: 10.1109/Tcsii.2012.2231015  0.779
2012 Jeon J, Hutin L, Jevtić R, Liu N, Chen Y, Nathanael R, Kwon W, Spencer M, Alon E, Nikolić B, Liu TJK. Multiple-input relay design for more compact implementation of digital logic circuits Ieee Electron Device Letters. 33: 281-283. DOI: 10.1109/Led.2011.2177436  0.395
2011 Shin C, Damrongplasit N, Sun X, Tsukamoto Y, Nikolic B, Liu TJK. Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22-nm node Ieee Transactions On Electron Devices. 58: 1846-1854. DOI: 10.1109/Ted.2011.2139213  0.399
2011 Nikolić B, Park JH, Kwak J, Giraud B, Guo Z, Pang LT, Toh SO, Jevtić R, Qian K, Spanos C. Technology variability from a design perspective Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1996-2009. DOI: 10.1109/Tcsi.2011.2165389  0.752
2011 Vamvakos SD, Stojanović V, Nikolić B. Discrete-time, linear periodically time-variant phase-locked loop model for jitter analysis Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1211-1224. DOI: 10.1109/Tcsi.2010.2097694  0.754
2011 Toh SO, Guo Z, Liu TJK, Nikolić B. Characterization of dynamic SRAM stability in 45 nm CMOS Ieee Journal of Solid-State Circuits. 46: 2702-2712. DOI: 10.1109/Jssc.2011.2164300  0.774
2011 Park J, Richards B, Nikolic B. A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band Ieee Journal of Solid-State Circuits. 46: 2524-2534. DOI: 10.1109/Jssc.2011.2164137  0.553
2011 Shin C, Tsai CH, Wu MH, Chang CF, Liu YR, Kao CY, Lin GS, Chiu KL, Fu CS, Tsai CT, Liang CW, Nikolić B, Liu TJK. Quasi-planar bulk CMOS technology for improved SRAM scalability Solid-State Electronics. 65: 184-190. DOI: 10.1016/J.Sse.2011.06.022  0.367
2010 Liu HI, Richards B, Zakhor A, Nikolic B. Hardware implementation of block GC3 lossless compression algorithm for direct-write lithography systems Proceedings of Spie - the International Society For Optical Engineering. 7637. DOI: 10.1117/12.846447  0.37
2010 Carlson A, Guo Z, Balasubramanian S, Zlatanovici R, Liu TJK, Nikolić B. SRAM read/write margin enhancements using FinFETs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 887-900. DOI: 10.1109/Tvlsi.2009.2019279  0.771
2010 Dolecek L, Zhang Z, Anantharam V, Wainwright MJ, Nikolić B. Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes Ieee Transactions On Information Theory. 56: 181-201. DOI: 10.1109/Tit.2009.2034781  0.561
2010 Zhang Z, Anantharam V, Wainwright MJ, Nikolić B. An efficient 10GBASE-T ethernet LDPC decoder design with low error floors Ieee Journal of Solid-State Circuits. 45: 843-855. DOI: 10.1109/Jssc.2010.2042255  0.613
2010 Tsai J, Toh SO, Guo Z, Pang LT, Liu TJK, Nikolic B. SRAM stability characterization using tunable ring oscillators in 45nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 354-355. DOI: 10.1109/ISSCC.2010.5433820  0.759
2010 Wang LTN, Xu N, Toh SO, Neureuther AR, King Liu TJ, Nikolic B. Parameter-specific ring oscillator for process monitoring at the 45 nm node Proceedings of the Custom Integrated Circuits Conference. DOI: 10.1109/CICC.2010.5617624  0.751
2009 Wang LTN, Panga LT, Neureuther AR, Nikolic B. Parameter-specific electronic measurement and analysis of sources of variation using ring oscillators Proceedings of Spie - the International Society For Optical Engineering. 7275. DOI: 10.1117/12.814227  0.337
2009 Qian K, Nikolic B, Spanos CJ. Hierarchical modeling of spatial variability with a 45nm example Proceedings of Spie - the International Society For Optical Engineering. 7275. DOI: 10.1117/12.814226  0.357
2009 Guo Z, Carlson A, Pang LT, Duong KT, Liu TJK, Nikolić B. Large-scale SRAM variability characterization in 45 nm CMOS Ieee Journal of Solid-State Circuits. 44: 3174-3192. DOI: 10.1109/Jssc.2009.2032698  0.685
2009 Pang LT, Qian K, Spanos CJ, Nikolic B. Measurement and analysis of variability in 45 nm strained-Si CMOS technology Ieee Journal of Solid-State Circuits. 44: 2233-2243. DOI: 10.1109/Jssc.2009.2022217  0.686
2009 Pang LT, Nikolić B. Measurements and analysis of process variability in 90 nm CMOS Ieee Journal of Solid-State Circuits. 44: 1655-1663. DOI: 10.1109/Jssc.2009.2015789  0.715
2009 Zlatanovici R, Kao S, Nikolic B. Energy-delay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design example Ieee Journal of Solid-State Circuits. 44: 569-583. DOI: 10.1109/Jssc.2008.2010795  0.769
2009 Dolecek L, Lee P, Zhang Z, Anantharam V, Nikolic B, Wainwright M. Predicting error floors of structured LDPC codes: Deterministic bounds and estimates Ieee Journal On Selected Areas in Communications. 27: 908-917. DOI: 10.1109/Jsac.2009.090809  0.559
2008 Wang LTN, Poppe WJ, Pang LT, Neureuther AR, Alon E, Nikolic B. Hypersensitive parameter-identifying ring oscillators for lithography process monitoring Proceedings of Spie - the International Society For Optical Engineering. 6925. DOI: 10.1117/12.773184  0.682
2008 Guo Z, Carlson A, Pang LT, Duong K, Liu TJK, Nikolic B. Large-scale read/write margin measurement in 45nm CMOS SRAM arrays Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 42-43. DOI: 10.1109/VLSIC.2008.4585944  0.64
2008 Nikolic B. Design in the Power-Limited Scaling Regime Ieee Transactions On Electron Devices. 55: 71-83. DOI: 10.1109/Ted.2007.911350  0.381
2007 Liu HI, Dai V, Zakhor A, Nikolić B. Reduced complexity compression algorithms for direct-write maskless lithography systems Journal of Micro/Nanolithography, Mems, and Moems. 6. DOI: 10.1117/1.2435202  0.33
2007 Marković D, Nikolić B, Brodersen RW. Power and area minimization for multidimensional signal processing Ieee Journal of Solid-State Circuits. 42: 922-934. DOI: 10.1109/Jssc.2007.892191  0.38
2006 Zlatanovici R, Nikolic B. Power – Performance Optimization for Custom Digital Circuits Journal of Low Power Electronics. 2: 113-120. DOI: 10.1166/Jolpe.2006.013  0.754
2006 Tsang CW, Chiu Y, Nikolic B. A 1.2V, 10.8mW, 500kHz sigma-delta modulator with 84dB SNDR and 96dB SFDR Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 162-163.  0.67
2006 Kao S, Zlatanovici R, Nikolic B. A 240ps 64b carry-lookahead adder in 90nm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 438+435.  0.754
2004 Ishihara F, Sheikh F, Nikolic B. Level conversion for dual-supply systems Ieee Transactions On Very Large Scale Integration Systems. 12: 185-195. DOI: 10.1109/Tvlsi.2003.821548  0.604
2004 Lynch R, Kurtas EM, Kuznetsov A, Yeo E, Nikolić B. The Search for a Practical Iterative Detector for Magnetic Recording Ieee Transactions On Magnetics. 40: 213-218. DOI: 10.1109/Tmag.2003.821194  0.568
2004 Chiu Y, Tsang CW, Nikolić B, Gray PR. Least mean square adaptive digital background calibration of pipelined analog-to-digital converters Ieee Transactions On Circuits and Systems I: Regular Papers. 51: 38-46. DOI: 10.1109/Tcsi.2003.821306  0.698
2004 Chiu Y, Gray PR, Nikolić B. A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR Ieee Journal of Solid-State Circuits. 39: 2139-2151. DOI: 10.1109/Jssc.2004.836232  0.408
2004 Marković D, Stojanović V, Nikolić B, Horowitz MA, Brodersen RW. Methods for true energy-performance optimization Ieee Journal of Solid-State Circuits. 39: 1282-1293. DOI: 10.1109/Jssc.2004.831796  0.357
2003 Nikolic B, Chang L, King T. Performance of Deeply-Scaled, Power-Constrained Circuits The Japan Society of Applied Physics. DOI: 10.7567/Ssdm.2003.G-2-1  0.34
2003 Yeo E, Augsburger SA, Davis WR, Nikolić B. A 500-Mb/s soft-output Viterbi decoder Ieee Journal of Solid-State Circuits. 38: 1234-1241. DOI: 10.1109/Jssc.2003.813250  0.628
2001 Leung M, Nikolic B, Fu LK, Jeon T. Reduced complexity sequence detection for high-order partial response channels Ieee Journal On Selected Areas in Communications. 19: 649-661. DOI: 10.1109/49.920173  0.337
2001 Nikolic B, Leung MM, Fu LK. Rate 8/9 sliding block distance-enhancing code with stationary detector Ieee Transactions On Magnetics. 37: 1168-1174. DOI: 10.1109/20.920493  0.308
2000 Maksimovic D, Oklobdzija VG, Nikolic B, Current KW. Clocked CMOS adiabatic logic with integrated single-phase power-clock supply Ieee Transactions On Very Large Scale Integration Systems. 8: 460-463. DOI: 10.1109/92.863629  0.365
2000 Nikolic B, Oklobdzija VG, Stojanovic V, Jia W, Chiu JK, Leung MM. Improved sense-amplifier-based flip-flop: design and measurements Ieee Journal of Solid-State Circuits. 35: 876-884. DOI: 10.1109/4.845191  0.373
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