Mani Soma - US grants

The proposed research is on fault modeling and test generation for mixed signal integrated circuits. In the area of fault models, defect and yield statistics are being used to derive comprehensive fault models for analog circuits. These include functional fault models useable in design for test and test generation. New test generation algorithms are being derived for analog circuits, and techniques are being developed to interface the analog tests with the digital circuitry in a mixed signal circuit. The fundamental theories are being validated experimentally with designs and data from industry.

This Industry/University Cooperative Research Fellowship project funds the University of Washington's Industry/University Cooperative Research Center for Design of Analog-Digital Integrated Circuits to study the design and test of mixed-signal systems at Boeing Company. The project which is to take from six to nine months is being cost-shared by Boeing with approximately 25% of the cost being provided by the University of Washington. The project is focussing on design-for-test methodologies for analog microcircuits, as the first step towards general analog test and diagnosis problems. Theoretical and experimental approaches will be applied to analog filters to prove the feasibility of the methodologies. The project has been endorsed by the Industry/University Cooperative Research Center for Design Analog-Digital Integrated Circuits. The Program Manager recommends the University of Washington be awarded $25,266 six months for this project.

EEC-9700705 ABSTRACT This award provides funding to the University of Washington, under the direction of Dr. Minoru Taya, for the support of a Combined Research-Curriculum Development project entitled, "Electronic Packaging and Materials." This project's goals are to establish an interdisciplinary research-curriculum on electronic packaging and materials (EPM) at the University of Washington. A curriculum of four courses with materials supplemented by new research results will be designed for teaching advanced undergraduate and first-year graduate students as well as engineers from local and regional industries as a part of the existing Televised Instruction in Engineering (TIE) system.

This joint work between Prof. Mani Soma (U. of Washington) and Jacob Abraham (U. of Texas). The research is on fault models, test generation, and design verification for analog and mixed-signal Integrated circuits. A top-down approach to test and verification in mixed-signal design is being pursued. Research topics include the following. Develop algorithms for abstracting a circuit from the description of a mixed-signal circuit. Define testability figures of merit for major analog blocks such as converters, filters, etc., and develop methods to compute them. Investigate algorithms to evaluate testability of mixed-signal design using high level design information. For design verification, the group is finding accurate transformation algorithms to map analog blocks to discretized form. Also, abstractions to reduce state space complexity during verification are being explored. The algorithms and methods are being built into testability and test tools.

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Scott A. Hauk
University of Washington

CISE Research Infrastructure: An Infrastructure for Integrated Systems Education and Innovation

The research contained in this proposal represents a wide-ranging investigation into the future of single-chip systems. We will seek to develop a design methodology that can provide the benefits of multiple different resource types for numerous design domains. To support the design of such cutting-edge silicon systems, we will develop innovative techniques to handle numerous design issues. These will include investigations into the following critical issues in chip design: Development of techniques for integrating RF and Analog components into future 1V SoC designs. Creation of high-performance, power efficient digital logic families for supporting the stringent requirements of these systems. Investigation into reconfigurable subsystems for SoC designs, providing post-fabrication customization for support of multi-protocol and multi-algorithm systems. Integrated testing methodologies for complex, heterogeneous systems that can provide complete system test. Complete simulation and design methodologies that can handle complete system integration, architectural exploration, and validation. In addition to the development of new approaches to future chip design, we will also develop innovative techniques for educating future chip designers. By providing an integrated curriculum in VLSI/CAD, embedded systems, and complex system design, we will help create system architects capable of harnessing these radically new design techniques and opportunities. We will also seek to increase the opportunities in chip design for new constituents, especially under-represented groups to help increase the pipeline of new designers

The primary driver of the information revolution is advanced silicon processing. Consequently, system design is undergoing a fundamental change, moving from multiple chip solutions to system-on-a-chip (SOC) solutions. However, as was noted in the National Science Foundation's recent planning workshops on advanced VLSI systems, the testing and measurement thoery and practice related to these heterogeneous resources integrated into a SoC solution is a major unsolved problem that could greatly limit future advances.
The advancements in process technologies provide for radically new types of devices, with commensurate design challenges and test and measurement needs. An example of such a system currently under development at the UW is a human/machine transducer chip-Universal Transducer Chip, a single integrated system capable of providing a speech recognition interface to a ubiquitous wireless network. Such a system is likely to become the standard interface modality for a wide range of new applications, from smart homes and smart test benches to ubiquitous high-performance computing fabrics. However, to achieve this potential, there are multiple test and measurement issues that must be addressed:
o Radio frequency transceivers must be tested and characterized in the ISM (2.4GHz) and UNfl (5.6-5.8GHz) frequency bands for a broad range of emerging wireless standards
o Low power, high performance wireless hardware implementations must be tested and measurement techniques must be developed and validated for future SoC applications in the LMDS bands at 17GHz, and above
o Heterogeneous single-chip integration and test and measurement must be supported, allowing for the fabrication of RF, analog, high performance digital, and re-configurable subsystems within a single piece of silicon
The infrastructure contained in this proposal enables an investigation into the future of testing and measuring ultra-high-frequency SoC systems, years in advance of their commercialization. We will seek to develop and demonstrate a test and measurement methodology that can provide the benefits of multiple different resource types for numerous design domains. As an initial driver of these efforts, we will characterize a Human/Machine transducer chip, seeking to guide the development of future system-on-a-chip design and test methodologies. It is generally representative of future SoC systems that will operate at ever higher frequencies with ever-increasing levels of complexity. To support the design of such cutting-edge silicon systems, we will develop innovative techniques to handle numerous test issues:
o Validation of techniques for integrating RF and Analog components into future ultra-low-voltage SoC designs.
o Validation of high-performance, power efficient digital logic families for supporting these systems.
o Integrated testing methodologies for complex, heterogeneous systems that can provide complete system test through an optimum combination of on-chip and off-chip ultra-high-frequency test environments.
In addition to the development of new approaches for testing and measuring SoC chip designs, we will also develop innovative techniques for educating future high-frequency SoC designers. By providing an integrated curriculum including high-frequency test and measurement, along with a just-in-time learning environment, we will help create system architects capable of harnessing these radically new design techniques and opportunities.

Recent developments in mixed-signal systems, especially those integrating computing and
communication in a system-on-a-chip, have focused on the goal to communicate information via wireless devices and networks. While digital system design to process baseband information is moving into the low gigahertz (GHz) frequency range, the mixed-signal transceivers have to operate in the ISM bands (2.5 GHz up to 5.8 GHz) with even higher frequencies in the near future to satisfy bandwidth demands. Analog design advances have produced several transceiver designs up to 5 GHz, using CMOS, BiCMOS, and other technologies. To reduce noise, these designs tend to separate the transmitter and receiver, and so far, have provided only a single physical link (one transmitter and one receiver) in a wireless device. In the design area, this proposal addresses the creation and verification of scalable systematic design methods to integrate two or more physical links on one single chip to provide more bandwidth and flexibility in communication applications. A methodology to incorporate multi-links is scalable in the sense that more links can be added by application demands. To create this methodology, we propose the following design approaches:

1. Noise cancellation techniques and circuits to deal with digital switching noise.

2. Noise cancellation techniques and circuits to deal with RF noise interference between different transceiver links and circuits.

These circuits will be validated using case studies from industry with whom we have had close
collaborations: Texas Instruments, Motorola, and National Semiconductors, who will provide
advanced fabrication technologies and simulation models for this study.
The designs will be fully tested and the development of scalable test methods is the second focus of this proposal. Mixed-signal test advances, despite intense activities, have been rather slow, especially in high-frequency (GHz) test. We propose to investigate the following approaches and distill the results into a test methodology that can be scaled with respect to operating frequencies and process advances:

1. End-to-end digital test methods using one transmit link and one receive link on the same chip
to verify correct information transmission.

2. Designs of on-chip delay and phase measurement circuits, operating at the same frequency as
the transceivers.

3. Interface between ATE and on-chip test circuits to use test resources efficiently.
During the validation of these test methodologies, we will need access to advance test equipment for comparison purposes, and these equipment will be provided by our collaborator at Teradyne (Tualatin, OR) and Wavecrest (San Jose, CA).

Another level of integration involves the curriculum - research aspects of the proposed work,
which is being implemented in our current curriculum revision. Dissemination approaches re-used the distance learning methods and assessment supported by NSF, FIPSE, and our own
university. The proposal will deliver fundamental methodologies and techniques, and train the
first-generation system architects in high-frequency mixed-signal design and test.