Matthew Karl Farrens, Ph.D. - Publications

Affiliations: 
University of California, Davis, Davis, CA 
Area:
integrated circuits

48 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Hanford N, Ahuja V, Farrens M, Ghosal D, Balman M, Pouyoul E, Tierney B. Improving network performance on multicore systems: Impact of core affinities on high throughput flows Future Generation Computer Systems. 56: 277-283. DOI: 10.1016/J.Future.2015.09.012  1
2015 Gegan RK, Archibald R, Farrens MK, Ghosal D. Performance analysis of real-time covert timing channel detection using a parallel system Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 9408: 519-530. DOI: 10.1007/978-3-319-25645-0_40  1
2014 Hanford N, Ahuja V, Farrens MK, Ghosal D, Balman M, Pouyoul E, Tierney B. Impact of the end-system and affinities on the throughput of high-speed flows Ancs 2014 - 10th 2014 Acm/Ieee Symposium On Architectures For Networking and Communications Systems. 259-260. DOI: 10.1145/2658260.2661772  1
2014 Congdon PT, Mohapatra P, Farrens M, Akella V. Simultaneously reducing latency and power consumption in openflow switches Ieee/Acm Transactions On Networking. 22: 1007-1020. DOI: 10.1109/Tnet.2013.2270436  1
2014 Macdonald K, Nitta C, Farrens M, Akella V. PDG-GEN: A methodology for fast and accurate simulation of on-chip networks Ieee Transactions On Computers. 63: 650-663. DOI: 10.1109/Tc.2012.140  1
2014 Hanford N, Ahuja V, Farrens M, Ghosal D, Balman M, Pouyoul E, Tierney B. Analysis of the effect of core affinity on high-throughput flows Proceedings of Ndm 2014: 4th International Workshop On Network-Aware Data Management - Held in Conjunction With Sc 2014: the International Conference For High Performance Computing, Networking, Storage and Analysis. 9-15. DOI: 10.1109/NDM.2014.10  1
2013 Nitta CJ, Farrens MK, Akella V. On-chip photonic interconnects: A computer architect's perspective Synthesis Lectures On Computer Architecture. 27: 1-113. DOI: 10.2200/S00537ED1V01Y201309CAC027  1
2013 Hanford N, Ahuja V, Balman M, Farrens MK, Ghosal D, Pouyoul E, Tierney B. Characterizing the impact of end-system affinities on the end-to-end performance of high-speed flows Proc. of Ndm 2013: 3rd Int. Workshop On Network-Aware Data Management - Held in Conjunction With Sc 2013: the Int. Conference For High Performance Computing, Networking, Storage and Analysis. DOI: 10.1145/2534695.2534697  1
2013 Farrens M. Message from the general chair Micro 2013 - Proceedings of the 46th Annual Ieee/Acm International Symposium On Microarchitecture. vii.  1
2012 Ahuja V, Farrens M, Ghosal D. Cache-aware affinitization on commodity multicores for high-speed network flows Ancs 2012 - Proceedings of the 8th Acm/Ieee Symposium On Architectures For Networking and Communications Systems. 39-48. DOI: 10.1145/2396556.2396564  1
2012 Nitta C, Farrens M, Akella V. DCOFAn arbitration free directly connected optical fabric Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 2: 169-182. DOI: 10.1109/Jetcas.2012.2193842  1
2012 Nitta C, Farrens M, Akella V. DCAF - A directly connected arbitration-free photonic crossbar for energy-efficient high performance computing Proceedings of the 2012 Ieee 26th International Parallel and Distributed Processing Symposium, Ipdps 2012. 1144-1155. DOI: 10.1109/IPDPS.2012.105  1
2012 Ahuja V, Ghosal D, Farrens M. Minimizing the data transfer time using multicore end-system aware flow bifurcation Proceedings - 12th Ieee/Acm International Symposium On Cluster, Cloud and Grid Computing, Ccgrid 2012. 595-602. DOI: 10.1109/CCGrid.2012.54  1
2011 Nitta CJ, Farrens MK, Akella V. Resilient microring resonator based photonic networks Proceedings of the Annual International Symposium On Microarchitecture, Micro. 95-104. DOI: 10.1145/2155620.2155632  1
2011 Nitta C, Farrens M, MacDonald K, Akella V. Inferring packet dependencies to improve trace based simulation of on-chip networks Nocs 2011: the 5th Acm/Ieee International Symposium On Networks-On-Chip. 153-160. DOI: 10.1145/1999946.1999971  1
2011 Ahuja V, Banerjee A, Farrens M, Ghosal D, Serazzi G. Introspective end-system modeling to optimize the transfer time of rate based protocols Proceedings of the Ieee International Symposium On High Performance Distributed Computing. 61-72. DOI: 10.1145/1996130.1996140  1
2011 Nitta C, Farrens M, Akella V. Addressing system-level trimming issues in on-chip nanophotonic networks Proceedings - International Symposium On High-Performance Computer Architecture. 122-131. DOI: 10.1109/HPCA.2011.5749722  1
2010 Mejia PV, Amirtharajah R, Farrens MK, Akella V. Performance evaluation of a multicore system with optically connected memory modules Nocs 2010 - the 4th Acm/Ieee International Symposium On Networks-On-Chip. 215-222. DOI: 10.1109/NOCS.2010.31  1
2008 Congdon P, Farrens M, Mohapatra P. Packet prediction for speculative cut-through switching Proceedings of the 4th Acm/Ieee Symposium On Architectures For Networking and Communications Systems, Ancs '08. 99-108. DOI: 10.1145/1477942.1477957  1
2008 Nitta C, Farrens M. Techniques for increasing effective data bandwidth 26th Ieee International Conference On Computer Design 2008, Iccd. 514-519. DOI: 10.1109/ICCD.2008.4751909  1
2008 Hadke A, Benavides T, Amirtharajah R, Farrens M, Akella V. Design and evaluation of an optical CPU-DRAM interconnect 26th Ieee International Conference On Computer Design 2008, Iccd. 492-497. DOI: 10.1109/ICCD.2008.4751906  1
2002 Oskin M, Chong FT, Farrens M. Using statistical and symbolic simulation for microprocessor performance evaluation Journal of Instruction-Level Parallelism. 4.  1
2001 Lee HHS, Tyson GS, Farrens MK. Improving bandwidth utilization using Eager Writeback Journal of Instruction-Level Parallelism. 3.  1
2000 Rich KD, Farrens MK. The decoupled-style prefetch architecture Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1900: 989-993.  1
2000 Rich KD, Farrens MK. Code partitioning in decoupled compilers Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 1900: 1008-1017.  1
2000 Lee HHS, Tyson GS, Farrens MK. Eager writeback - a technique for improving bandwidth utilization Proceedings of the Annual International Symposium On Microarchitecture. 11-21.  1
2000 Haungs M, Sallee P, Farrens M. Branch transition rate: A new metric for improved branch classification analysis Ieee High-Performance Computer Architecture Symposium Proceedings. 241-250.  1
2000 Oskin M, Chong FT, Farrens M. HLS: Combining statistical and symbolic simulation to guide microprocessor designs Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 71-82.  1
1999 Oskin M, Hensley J, Keen D, Chong FT, Farrens M, Chopra A. Exploiting ILP in page-based intelligent memory Proceedings of the Annual International Symposium On Microarchitecture. 208-218.  1
1998 Rivers JA, Tam ES, Tyson GS, Davidson ES, Farrens M. Utilizing reuse information in data cache management Proceedings of the International Conference On Supercomputing. 449-456.  1
1997 Tyson G, Farrens M, Matthews J, Pleszkun AR. Managing data caches using selective cache line replacement International Journal of Parallel Programming. 25: 213-242. DOI: 10.1007/Bf02700036  1
1996 Tyson G, Farrens M. Evaluating the effects of predicated execution on branch prediction1 International Journal of Parallel Programming. 24: 159-186. DOI: 10.1007/Bf03356746  1
1995 Tyson G, Farrens M, Matthews J, Pleszkun AR. Modified approach to data cache management Proceedings of the Annual International Symposium On Microarchitecture. 93-103.  1
1994 Tyson G, Farrens M. Techniques for extracting instruction level parallelism on MIMD architectures Proceedings of the Annual International Symposium On Microarchitecture. 128-137. DOI: 10.1109/MICRO.1994.717450  1
1994 Tyson G, Farrens M. Code scheduling for multiple instruction stream architectures International Journal of Parallel Programming. 22: 243-272. DOI: 10.1007/Bf02577734  1
1994 Farrens M, Tyson G, Pleszkun AR. Study of single-chip processor/cache organizations for large numbers of transistors Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 338-347.  1
1994 Farrens MK, Ng P, Nico P. Comparison of superscalar and decoupled access/execute architectures Proceedings of the Annual International Symposium On Microarchitecture. 100-103.  1
1993 Farrens M, Park A, Fanfelle R, Ng P, Tyson G. Partitioned translation lookaside buffer approach to reducing address bandwidth Proceedings of the Ninth Annual International Symposium On Computer Architecture. 435.  1
1992 Farrens M, Park A, Tyson G. Modifying VM hardware to reduce address pin requirements Proceedings of the 25th Annual International Symposium On Microarchitecture. 210-213.  1
1992 Tyson G, Farrens M, Pleszkun AR. MISC. A Multiple Instruction Stream Computer Proceedings of the 25th Annual International Symposium On Microarchitecture. 193-196.  1
1992 Farrens M, Park A, Woodruff A. CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension Proceedings of the International Conference On Parallel Processing. 573-577.  1
1992 Farrens M, Park A, Fanfelle R, Ng P, Tyson G. A partitioned translation lookaside buffer approach to reducing address bandwidth Conference Proceedings - Annual Symposium On Computer Architecture. 435.  1
1991 Farrens MK, Pleszkun AR. Implementation of the PIPE Processor Computer. 24: 65-70. DOI: 10.1109/2.67195  1
1991 Farrens M, Wetmore B, Woodruff A. Alleviation of tree saturation in multistage interconnection networks . 400-409.  1
1991 Farrens MK, Pleszkun AR. Strategies for achieving improved processor throughput Conference Proceedings - Annual Symposium On Computer Architecture. 362-369.  1
1991 Farrens M, Park A. Dynamic base register caching: A technique for reducing address bus width Conference Proceedings - Annual Symposium On Computer Architecture. 128-137.  1
1989 Farrens MK, Pleszkun AR. Improving performance of small on-chip instruction caches Conference Proceedings - Annual Symposium On Computer Architecture. 234-241.  1
1986 Pleszkun AR, Farrens MK. INSTRUCTION CACHE DESIGN FOR USE WITH A DELAYED BRANCH . 73-88.  1
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