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Baris Arslan, Ph.D. - Publications

Affiliations: 
2013 Computer Science and Engineering University of California, San Diego, La Jolla, CA 
Area:
Computer Science, Computer Engineering
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14 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Arslan B, Orailoglu A. Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 2093-2103. DOI: 10.1109/Tcad.2016.2535902  0.695
2016 Arslan B, Orailoglu A. Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 141-154. DOI: 10.1109/Tcad.2015.2448689  0.658
2013 Arslan B, Orailoglu A. Tracing the best test mix through multi-variate quality tracking Proceedings of the Ieee Vlsi Test Symposium. DOI: 10.1109/VTS.2013.6548886  0.699
2013 Arslan B, Orailoglu A. Full exploitation of process variation space for continuous delivery of optimal delay test quality Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 552-557. DOI: 10.1109/ASPDAC.2013.6509654  0.67
2012 Arslan B, Orailoglu A. Delay test resource allocation and scheduling for multiple frequency domains Proceedings of the Ieee Vlsi Test Symposium. 114-119. DOI: 10.1109/VTS.2012.6231089  0.614
2011 Arslan B, Orailoglu A. Adaptive test framework for achieving target test quality at minimal cost Proceedings of the Asian Test Symposium. 323-328. DOI: 10.1109/ATS.2011.91  0.684
2011 Arslan B, Orailoglu A. Adaptive test optimization through real time learning of test effectiveness Proceedings -Design, Automation and Test in Europe, Date. 1430-1435.  0.689
2010 Arslan B, Orailoglu A. Delay test quality maximization through process-aware selection of test set size Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 390-395. DOI: 10.1109/ICCD.2010.5647687  0.662
2004 Arslan B, Orailoglu A. Circularscan: A scan architecture for test cost reduction Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1290-1295. DOI: 10.1109/DATE.2004.1269073  0.667
2004 Arslan B, Orailoglu A. Test cost reduction through a reconfigurable scan architecture Proceedings - International Test Conference. 945-952.  0.665
2004 Arslan B, Orailoglu A. Design space exploration for aggressive test cost reduction in Circular Scan architectures Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 726-731.  0.687
2004 Arslan B, Sinanoglu O, Orailoglu A. Extending the applicability of parallel-serial scan designs Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 200-203.  0.668
2003 Arslan B, Orailoglu A. Extracting precise diagnosis of bridging faults from stuck-at fault information Proceedings of the Asian Test Symposium. 2003: 230-235. DOI: 10.1109/ATS.2003.1250815  0.507
2002 Arslan B, Orailoglu A. Fault dictionary size reduction through test response superposition Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 480-485.  0.559
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